This paper will demonstrate the effect high reflow temperatures in lead free processes will have on the reliability of printed
circuit boards from a broad range of laminate materials for both traditional and lead-free processes. The focus will be on 24
layer boards of high thickness (3.2 mm) and high aspect ratios (5.21:1 and 10.42:1). The test boards were preconditioned
through six reflow cycles to simulate assembly and rework processes for both traditional and lead-free processes and then
tested using IST.
The results showed that raising the reflow temperatures from standard tin-lead to lead-free had a significant effect on the
reliability of PTVs,regardless of the laminate materials used. The results also showed that traditional and even some leadfree
materials did not survive the temperature increase when measured against industry standards.

Motorola has been using embedded polymer thick film resistors on immersion silver-plated copper terminations in products
for four years,and in the past year other firms have begun using this technology in their products. It is available to any
electronic equipment maker from multiple board suppliers. Highly reliable resistors with values ranging from ohms to megaohms
can be embedded in conventional HDI/FR-4 multilayer boards,providing cost savings and product size reduction. In
this paper we present recent improvements in resistor materials and design. Resistor value predictability is improved with a
simple innovation in termination design and the segmenting of low aspect ratio resistors. Resistor value distributions are
improved with more thixotropic inks. Combined,these improvements allow 10-20% untrimmed tolerances (depending on ink
resistance and production volume) for 0.25-mm-wide resistors. Tighter tolerances are possible with laser trimming.

Novel configurations of decoupling capacitors were formed by anodizing Ta,resulting in Ta2O5 films 2000 Å thick and k =
23,giving about 110 nF/cm2. Since the dielectric is very thin,the parasitic inductance is almost unmeasurable,and is shown
by simulation to be less than 1 pH/square. Breakdown voltages are around 30 V and leakage at 5 V is less than 0.1 µA/cm2.
The total ESR is dependent on the plate thickness,but can be less than 10 mO. Since the material is paraelectric,there is no
significant falloff of dielectric behavior at frequencies well over 10 GHz. The capacitors are formed on flex with closespaced,
alternating contacts to minimize contact inductance. The assemblies are designed to be included in a polymer-based
BGA stack to provide ultra-low inductance as close to the chip as possible. In this presentation,the reasons for using these
materials and configurations are presented from the point of view of electronic performance,reliability,and
manufacturability.

We have previously published our work on developing thin substrates for use as embedded capacitor layers. Based on this
work we have continued to characterize the performance and reliability of these materials.
We will discuss the experiences of PCB shops in processing the material and review the results of the various reliability
studies. Also,additional test vehicles have been processed for testing at high frequencies.
Customers have requested even higher capacitance values. We continue to work on making thinner dielectrics,and thus raise
capacitance,but it is believed that loading the polymer with high dielectric (Ferroelectric) particles will provide the best
values for this type of capacitor. We will exam the effect of loading the polymer with High Dk particles and compare the
positive and negative aspects of using filler.
The results of our internal and external testing (and a comparison to existing and developing capacitor materials) will help
determine what benefit(s),if any,a high speed system would get by using a high Dk filler polymer substrate.

The newly developed Ohmega-Ply “Resistor-Built-in-Trace” technology uses low-ohmic resistive materials for embedded
resistors congruent to the circuitry in a multilayer PCB or HDI substrate. High frequencies and miniaturization has created
the need for miniature resistors. Until now,the paradigm of the shape of an embedded resistor was the same as an SMT
resistor,a discrete-like component having a definite width and length and occupying space. The new “built-in-trace”
technology uses the signal path itself for the resistor and,therefore,requires no additional board area,thereby enabling higher
I/O and component densities and reduced form factors. A “virtual component” is created by the gap in the conducting trace
crossed only by the thin-film low ohmic resistive layer. No terminating conductive pads are required,the trace merely
continues along its path. The CAD layout is simplified by the elimination of the resistor footprint. Low ohmic materials of 10
ohms per square or less yield tight tolerance of 3% or less so that the tolerance of the resistive element is equal to or better
than the tolerance of the characteristic impedance of the circuit trace thereby improving signal integrity. The equivalency of
the resistor width and trace width tolerances means that any manufacturing process capable of producing a controlled
impedance PCB will be capable of producing the built-in-trace resistors to the required tolerance without resistor trim.

This paper will discuss the use of thin film buried resistors and thin core plane pairs in high layer count high reliability
printed wiring boards used in single and double sided surface mount assemblies. Very high thermal stress durability is
required for assembly and component repair/replacement. The high density multilayer and sequential built designs of 14-26
layers use a combination of buried vias,blind vias,thin cores,several layers of buried resistors and thin core plane pairs to
meet controlled impedance and circuit performance. The design of the resistors for BGA pull down terminations and for incircuit
resistors contain various values and tolerances. Overall thermal performance of the board is critical to the product
reliability requiring the buried resistors and thin core plane pairs to also survive extreme thermal exposure. Thermal stress
testing,as required by the applicable standard,was extended to multiple times in order to determine product robustness for
laminate defects,plating integrity and inner plane connection durability. In addition,Current Induced Thermal Cycling
Testing can be performed for comparative analysis. Special test coupons can be designed that duplicate the actual conditions
of the board and allow the buried resistor layer to be present in the microsection for evaluation during the required
inspections. As with conventional printed wiring technology,failures do occur,but typically only after extreme thermal stress
or rework. Failure analysis was performed to identify the cause. Pictorial views of the component density,resistor designs,
layer stackup,and failure analysis activity are contained in the paper. This paper will show that embedded passive technology
can be implemented with success for high density,high layer count and high reliability printed wiring boards.

Embedded passives technologies can provide benefits of size,performance,cost,and reliability to high density,highspeed
designs. A number of embedded passive technology solutions are available to the designer. Based on our
experience with Shipley’s thin-film,high-ohmic,InSiteTM embedded resistor materials (500 and 1000 O/ ?),this paper
provides some guidelines for selecting the appropriate embedded resistor technology and implementing it at a board
fabricator. The design of embedded resistors,and the trade-offs between resistor size,tolerance,and capability of board
fabrication processes,are analyzed in detail. This paper also discusses selection of the appropriate embedded capacitor
technology and introduces some initial results on Shipley’s thin-film,high-Dk,InSite embedded capacitor material (200
nF/cm2). A simple cost analysis helps to screen which designs are appropriate candidates for embedded technology from
a cost justification point of view.

Embedded passives,i.e.,resistors and capacitors built right into the printed circuit board substrate,is a rapidly emerging and
pivotal technology for the PCB industry preceded only by the plated thru hole in the 50s and microvias in the 80s.
This paper is a presentation of the design process for embedding discrete resistors and capacitors into circuit board substrates.
Materials are available in a wide range of values and technologies. The paper includes a step-by-step process for designing
resistors and capacitors with a variety of materials and embedded passive technologies.
Performance,miniaturization,and cost are the drivers. The average cell phone has 445 SMT passive components at a 25:1
ratio to ICs. Embedding many of these will improve performance,enable more functionality and reduce cost per function.
Embedded passives are not limited to cell phones. Many other applications will benefit from improved performance. Several
materials are commercially available today and many new materials are in development. The paper also includes a brief
review of these materials.

This paper discusses the work and testing performed to obtain extreme high reliability performance from high layer count,
large panel format multilayer printed wiring boards that are used for backplanes in surface mount technology applications.
High density I/O surface mount connectors require fine lines,spacing and small vias. Couple this with a very large amount of
connectors and with a Printed Circuit Board (PCB) of 330mm (13”) by 990mm (39”),it results in very high layer count
Printed Circuit Board (PCB) that can be thirty seven layers and with resulting thickness of approximately 5.3mm (0.210”)
having aspect ratios up to 11:1. Surface mount assembly on a double-sided board requires two reflows which thermally stress
the product and have caused classic plated through hole failures (i.e. barrel fatigue) during initial assembly operations.
Additionally rework of connectors is a requirement that applies additional stress and can cause more failures. This paper will
show information on routing requirements that employ several layers of buried vias and thin 0.1mm (.004") cores and
multiple ground power planes used for voltage and impedance control. Early failures caused by thermal exposure lead to an
intensive development program to consider all aspects and variables in building a high reliability product. Material with
varying Tg and Z-axis properties were included in the tests along with variables in lamination adhesion,etchback,and
plating. A testing program was set up to include multiple thermal stress solder floats,a special plated through hole coupon for
thermal cycle testing and then Current Induced Thermal Cycling preceded by multiple assembly simulation thermal
exposures. Data accumulated will be reviewed with correlation made to the key items that produce the high reliability printed
wiring board. Supplier and user cooperation was key to making the result a successful product that is now in small volume
production. This knowledge can be useful to others who are considering high layer count large panel formats that required
assembly reflow soldering as an alternative to compliant pin technology.

Driving factors for the use of via in pad technology include the growing trend towards more dense and complex printed
circuit board designs as well as the need to minimize parasitic capacitance and inductance on high speed digital circuits.
These two driving factors are accompanied by the enhanced capability of printed circuit board suppliers to fabricate smaller
via diameters without increased fabrication cost. In this study via in pad technology is referring to the use of standard vias,
not microvia technology or blind via technology. Via diameters considered in this study include a range from 0.008” finished
hole diameter up to a 0.012” finished hole diameter. Reduced via hole size enhances the use of via in pad technology,
especially on smaller devices such as 0402 components. Via in pad technology creates increased printed circuit board (PCB)
routing space on the outer layers,which aids in the routing of complex printed circuit board designs. Via in pad technology
also reduces parasitic capacitance and inductance which are typically found in high speed digital circuits.1 This is
accomplished by eliminating the “stub trace” which is typically created by placing a second pad adjacent to the component
pad just to have a land for the via to be drilled.