The assembly of thinned silicon die (25-100µm) onto flex substrates provides options for ultra thin,flexible electronics for
applications ranging from smart cards to space-based radars. For high density applications,3-D modules can be fabricated by
stacking and laminating preassembled and tested flex layers then processing vertical interconnections. This paper describes
processes for flip chip assembly of thinned die to polyimide and liquid crystal polymer (LCP) flex substrates.
Two assembly approaches have been developed for use with polyimide and LCP flex substrates. In the first approach,the
solder bumped die are reflow soldered to the patterned flex. A fixture is required to maintain the flex substrate flat during
reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing
onto the top of the thin silicon die and will be discussed. In the second approach,vias are etched through the polyimide or
LCP,exposing the underside of the contact pads. Solder paste is squeegeed into the vias,reflowed and cleaned,creating
solder ’bumps’ in the via. Die with low profile solder bumps created by immersion soldering are fluxed,placed and reflowed.
The die is then underfilled. This approach produces a lower total assembly thickness.

Thermoset epoxies,discovered nearly 80 years ago,remain the workhorse materials for electronic packaging and printed
circuit boards,but this may change with increasing technical,economic and regulatory demands. Modern halogen-free
thermoplastics boast superior properties and automated high-efficiency high-volume processes. Injection molding can readily
produce intricate 3D structures suitable for packaging and 3D molded circuits. Although there is a well-established packaging
infrastructure geared to thermoset epoxies there is a much larger world-wide manufacturing base that excels in thermoplastics.
Nearly 16-billion pounds of thermoplastics are molded into parts each year in the USA alone; 30 times higher than for
epoxies. The time may be right for adding thermoplastic packages,interconnects and circuitry to 21st century electronics.
This paper will discuss concepts,novel designs,new processes and the advancements for injection molded packaging and
highlight their impressive attributes; the lowest moisture uptake,the fastest processing and the highest stability in the world
of polymers. While MEMS packaging will be a central theme,general component packaging will also be discussed including
power packages and camera modules. The discussion will include the development of new BGA concepts that utilize
automatic insert-molding of tiny metal balls to create the 1st and 2nd level interconnect system. Assembly topics will cover
package sealing methods that include laser welding.
New Multi-Chip Package (MCP) ideas based on insert-molded flex will be described that could find use in stackable designs.
Hermeticity is discussed using data to show that plastics are near-hermetic but do not yet pass MIL-STD levels. But,future
work with barrier coatings may eventually lead to a low cost full hermetic plastic package. And finally we’ll look at 3D
molded circuits,now called MID (Molded Interconnect Devices),and search for new applications. Conductor patterning
methods include molding with plating-catalyzed resin and direct laser writing. We will also consider the idea of combining
molded circuitry and packaging for maximum synergy.

Hand-held communication and entertainment products continue to dominate the consumer markets worldwide,and with each
generation,companies are offering more and more features and/or capability. Even though the actual functionality of the new
product offering expands,the customer is expecting each generation to be smaller and lighter that its predecessor. More
functionality typically requires additional or more complex electronics and greater memory capacity. Increasing functional
capability,however,can adversely impact the products size as well as manufacturing cost. The challenge manufactures face
when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations
within budget and without increasing product size.
This paper will explores a number of system level applications developed within Tessera’s Package Engineering Service
Laboratories and examine the results of extensive computer modeling as well as review the data compiled from electrical
performance and physical stress testing.

Meeting RoHS requirements is confusing at best. Currently,RoHS bans the presence of 6 substances,: Lead (Pb),Cadmium (Cd),Mercury (Hg),Hexavalent Chromium (Cr6+),Polybrominated biphenyl (PBB) and Polybrominated diphenylether (PBDE). As of 18 August 2005,the European Union (EU) amended the RoHS document with maximum concentration values (MCVs) of 1000 ppm for 5 of the substances; Pb,Hg,Cr6+,PBB & PBDE and 100 ppm for the 6th substance; Cd at the homogenous level. Other documents within the EU and member states have defined MCVs,but there is not total agreement between EU Directives and the member states on the maximum threshold values. With the delay of defined RoHS thresholds,other regions of the world are defining MCVs,but without universal agreement. Companies in the electrical and electronics equipment (EEE) industry are subsequently incorporating their understanding of MCVs into company specifications and requiring the suppliers to meet them.
What are the existing EU Directive requirements? How do they apply and what thresholds should be used for electrical and electronic products? This paper will discuss the RoHS 6 substances,thresholds as stated in the EU,common company defined threshold differences and the issues they cause. It is not all inclusive since laws and directives are constantly changing,evolving or being released.

This paper describes flexible printed circuit boards,used as “Product Boards” or “Interposers”,chip mounting structures. Traditionally,flexible circuit boards are made with polyimide dielectric cores. These are made either by lamination processes of a foil with adhesive,or the build-up of the copper from an “adhesiveless” process

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Hand-held communication and entertainment products continue to dominate the consumer markets worldwide and,with each generation,offering more and more features and/or capability. And even though the actual functionality of the new product offering expands,the customer is expecting each generation to be smaller and lighter that its predecessor. More functionality typically requires additional or more complex electronics and greater memory capacity. Increasing functional capability,however,can adversely impact the products size as well as manufacturing cost. The challenge manufactures face when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations within budget and without increasing product size. Increased electronic functionality can be achieved through the development of more complex silicon integration (system-on-chip) but that route generally requires a great deal of capital resources and time. With the rapid deployment of new products from an ever growing number of competing companies’,time-to-market can be the difference between leading and following. For that reason,many manufacturers will rely heavily on more innovative IC package solutions,solutions for integrating a number of already proven functional elements within a single-package outline. When adapting multiple die configurations,each package becomes a fully tested subsystem that can be certified by the supplier before board or module level assembly. To achieve system level integration and miniaturization goals,companies’ can now rely on a combination of multiple-die package solutions and high-density flexible film based substrate methodology. For many applications,the multiple-die package is actually proving superior to the system-on-chip alternative because it minimizes risk and economically integrates several different but complementary functions. In the case of memory for example,multiples of the same function can be vertically stacked for increased density. This paper will explore three flexible film based multiple die system level applications developed within Tessera’s Package Engineering Service Laboratories.

Recent advances in chip technologies have prompted a rapid increase in the density of solder joints in electronic components. Further reductions in pitch are likely,leading to joint structures exhibiting sub 0.100mm (100µm) dimensions. EC legislation from mid 2006 bans the use of Pb,for most applications,in solders which means that next generation solder pastes will have to be Pb-free. One low cost assembly solution is stencil printing/wafer bumping of fine particle solder pastes. For ultra fine pitch applications this will present significant challenges and there is a requirement to understand the sub processes in stencil printing at ultra fine pitch. Paste roll; aperture filling/release; post print behavior and paste open time have been examined using fine particle Pb-free solder pastes,and solder paste rheology,particle size distribution,metal content,flux type and stencil aperture attributes have been investigated to provide ultra fine pitch solutions. In this paper we report that solder paste printing has been achieved at sub 100µm pitch using Pb-free solder paste with IPC type-6 (15-5µm) and type-7 (12-2µm) particle size distributions. For the type-6 paste,full array printing was achieved with 50µm deposits at 110µm pitch,and for peripheral printing patterns,60µm sized deposits at 90µm pitch. For type-7 paste sub 100µm pitch printing was achieved for full array patterns. The results satisfy the criterion that paste deposits can be produced at ultra fine pitch. Furthermore,subtle differences in the performance of type-6 and type-7 suggest that each is suitable for different specific application geometries. Reflow trials indicated that solderability of the small volumes depended heavily on reflow profile ramp rates and reflow atmosphere. Process models for introducing inert nitrogen reflow atmospheres are presented.

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