The need for dynamic compact models for Integrated Circuits (ICs) is a well-recognized problem in electronics cooling
simulations of electronic systems. Simplified thermal models have been reported in literature to simulate steady-state and
transient thermal behavior of IC devices. Most of the simplification approaches require a pre-determined topology of a
resistance-capacitance (RC) network. Multigrid technique allows for automatically constructing both the topology and
characteristics of the reduced-order or compact models of devices (primarily IC packages) for use in system-level
simulations. In this study,we report an approach where the topology of RC networks is automatically generated. The
topology of the RC network is not predetermined and can be automatically changed to meet the modeling accuracy
requirement. The procedure is robust for packages with various degrees of complexity in both automatic construction of RC
network topology and automatic extraction of nodal RC values. The procedure is also applicable for complex IC sub-systems
or systems like multi-chip modules,stacked die package,system-in-package,and CPU module,and hard drives.
In the study report herein,the method is applied to a 196-pin fine pitch ball grid array (FBGA15x15_196L) package. An RC
network is created for the package and then used in a transient CFD simulation under single phase natural convective cooling
in JEDEC chamber. The simulation results using the RC network model are compared to the corresponding detailed package
simulation.

Microvias are the fastest growing new technology for printed circuits. Once you understand the basics,the advanced topics
bring the real advantage to light. This talk will highlight the procedures and conditions that designers needs to consider
making microvias the most productive and profitable architecture for their designs. These ideas go beyond the IPC standards,
but are essential for any designer using microvias. The talk will cover: Vendor Qualification,Component / Assembly issues,
Planning the Design,Signal Integrity concerns and Channel Routing procedures.

In most of today's high speed digital interconnects,the signal loss associated with the printed circuit board (PCB) is the
dominate factor. Material selection,trace geometry,and choice of copper foil all play a role in establishing the signal loss
associated with the PCB interconnect. Silicon and system designers have techniques for dealing with signal loss and
compensating for lossy interconnects; but,these techniques require accurate modeling and characterization of each source of
interconnect loss. Previous work has shown the impact of dielectric material selection on loss,as well as conductor loss due
to high frequency skin effects associated with copper roughness,copper foil tooth structures,and surface finish selection. For
innerlayer stripline traces,surface preparation processes such as oxide and oxide alternative alter the conductor surface to
improve adhesion. This alteration to the conductor surface geometry affects conductor loss and can influence suppliersupplier
variation. Furthermore oxide processing can affect lot to lot variation of impedance and line loss. This paper
investigates the differences between several oxide and oxide alternative processes on high frequency conductor loss and the
impact of process parameters such as rework.

Traditional reduced black oxide processes for inner layer bonding have been superseded by a newer generation of peroxidesulfuric
texturing processes. These lower cost processes,based on an organically controlled microetch,have proven to be
simpler,faster,and more energy efficient. They have eliminated traditional problems such as: re-oxidation caused by baking
and storage,high resistance shorts and pink ring defects.
However,the relentless trend of miniaturization and the inexorable pressures for cost reduction continue to push the
envelope. Lower etch factors are necessary for controlled impedance and fine line applications,and higher copper loadings
are a prerequisite for increased capacity / reduced cost of ownership. The paper describes the major challenges faced,and the
resulting technical progression which has been achieved,to evolve the next generation of high performance processes capable
of meeting this target.

PTFE material is very hydrophobic and among the most difficult to deposit electroless copper or direct metallization. These
materials have very low friction,which makes a surface non-wettable. Plasma technology has the ability to create wettable
through holes by removing fluorines from the surface,leaving the hole walls activated for metallizing. There are several
process gases used to treat PTFE material. Each gas has a different effect on surface wettability. Chemical etching also
changes the wettability of PTFE material by activating the surface.
Although both plasma technology and chemical etching render a wettable surface,there is a recovery time in which the PTFE
material returns to its original state due to fluorine migration. This paper evaluates the results of a DOE comparing three
plasma processes and chemical etching in relationship to wettability,recovery time and plating adhesion.

The technology shift toward higher performance (low Dk,low Df,faster signal speeds) resin materials for high reliability
high layer count multlayer interconnect devices is moving rapidly. PWB fabricators are discovering that the bond strength
between the copper circuitry and these resin systems is not as reliable with reduced oxide bonding treatments. It has been
shown in the market place that reduced oxide processes are being replaced by new process developments for a variety of
reasons that will be explained. In addition,increased use of ENIG (electroless nickel-immersion gold) and immersion tin
processes is causing adhesion failures of some liquid photoimageable soldermasks. This paper will explore the mechanism of
resin adhesion to copper surfaces and provide a discussion on the interaction of the key process parameters (etch rate,organic
coating content,sulfuric acid concentration,copper loading in solution) on the process performance. Reduced oxide bonding
technology will be the benchmark comparison for the performance of the alternative technology. Bond strengths for a variety
of high performance resin systems will be measured. These materials will include high Tg epoxy FR-4,cyanate ester,BT,
polyimide,PPE and PPO resins. In addition to measuring bond strengths,other methods including solder float and T-260
time to delamination will be utilized to compare results. Additional IPC recognized test methods would be employed to
compare the performance and reliability of the organo-metallic process to reduced oxide. The paper will conclude with a
discussion on improving soldermask adhesion with a modified organo-metallic surface treatment process.

This paper describes a copper electroplating enabling technology for filling microvias.
Driven by the need for faster,smaller and higher performance communication and electronic devices,build-up technology
incorporating microvias has emerged as a viable multilayer printed circuit manufacturing technology. Increased wiring
density,reduced line widths,smaller through-holes and microvias are all attributes of these High Density Interconnect (HDI)
packages.
Filling the microvias with conductive material allows the use of stacked vias and via in pad designs thereby facilitating
additional packaging density. Other potential design attributes include thermal management enhancement and benefits for
high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over
alternative via plugging techniques.
The features,development,scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling
processes,including chemistry and equipment,are described.

With an increasing number of designers specifying conductive material for plugging through-holes,a more robust process to
produce 100% fill is needed for the whole range of aspect ratios. With via sizes ranging from 8 to 20 mils in diameter and
board thicknesses approaching and sometimes exceeding 200 mils,a method to plug reliably and consistently with ease is
necessary for the future of the conductive filling process.
It is very common in the industry to use a vacuum table to assist in "pulling" the material into the through hole. Typically this
requires several passes with a squeegee to attempt to fill the through hole completely. Because this vacuum assist is enabled
throughout the process,air ingression is inevitable. Further aggravating this issue is the fact that many production houses still
squeegee this material by hand,offering no control over other important process parameters such as squeegee angle,speed
and pressure. The end result is an inconsistent process,with incomplete fill of the though-hole and large air pockets.
This paper will identify the process variables that affect the through hole fill quality and offer solutions to control them. It
will also investigate an alternative production method that eliminates the need for "vacuum pull" to draw the material (and
air) into the through hole. Rather it utilizes a "direct imaging" method that applies positive pressure within an enclosed print
head to press the material into the through hole while maintaining control over all process parameters. With this process,it is
now possible to fill through holes more quickly and efficiently,providing a more reliable process that enables a high-volume
application of conductive through-hole.

There is increased interest in the printed wiring board (PWB) industry with regards to the use of periodic pulse reverse (PPR)
plating to electroplate printed circuit boards. PPR plating offers several advantages over DC plating including improved
throwing power,reliability,and surface distribution,leading to decreased product cycle times,and increased throughput. The
use of widescale PPR plating in acid copper; however,has been hampered by disadvantages such as short bath life and a
limited ability to plate high aspect ratio (HAR) thick panels. To that end,an acid copper PPR chemistry has been developed
to address these issues. Scale-up,production testing,and the analytical techniques used to control the process are discussed
herein. The process capability with respect to high aspect ratio panels as well as mixed technology boards is also presented.

Colloidal graphite direct metalization processes have proven their usefulness as a replacement for electroless copper. This is
especially the case in high technology and quick turn applications. The consistency of colloidal graphite direct metalization
processes has been improved through a better understanding of the influence of contaminants. The contaminants cause
degradation of the colloid and thus reduce coating effectiveness. This paper will discuss the importance of reducing
contamination of the colloidal graphite. The benefits of a newer generation graphite colloid process will be highlighted.