Various test methods are used to characterize the PCB plated-thru-hole reliability. One such method is the Interconnect Stress
Test (IST). The results from this test are often used to qualify PCB materials and/or fabricators. This paper will discuss how
certain statistical analysis techniques may be used to decipher the results,and predict capabilities of PCB materials and/or
processes.

The selection and use of solder joint modification configurations for printed wiring assemblies has traditionally been a design
specific activity. The implementation and use of a standardized set of solder joint modification configurations on an industrywide
basis would be cost effective and promote industry consistent modification practices. A set of 14 commonly used IPC
Class 3 modification configurations were selected for investigation. Thermal cycle testing was chosen to evaluate the solder
joint thermal cycle fatigue reliability of the configuration set. A total of 1,972 thermal cycles using a -55ºC to +125ºC recipe
in accordance with the IPC-9701 guidelines were completed. Failure analysis and photo-documentation were conducted
characterizing modification configuration solder joint geometries and wetting angles. The investigation
results/recommendations were disseminated to the IPC-A-610 and IPC-7711/7722 specification committees for potential use.

A variety of mechanical and thermal stress related problems related to Flip Chip Ball Grid Array Packages (FCBGAs) are
often solved by the Finite Element Method. Often,the question for the stress analyst is how to simplify the problem at hand
and come up with a sufficiently accurate model in a reasonable amount of time. The aim of this paper is to examine several
different modeling strategies and compare the performance of various models so as to provide a guideline for selection of a
modeling strategy. For the comparison of various models,the problem of thermal cycling is addressed here. The comparison
of various models is based on strains in the critical solder ball. A common geometric layout is assumed. Properties of the
laminate are varied so as to cover the range of properties of various laminates available. Pros and cons of various
methodologies are pointed out and are expected to provide useful guidelines for the stress analysts in the electronic packaging
area. The paper shows that making meaningful comparisons and predictions using modeling requires in-depth knowledge
experience in the field of modeling as well as the physical phenomena being modeled.

A new,green epoxy mold compound has been developed to encapsulate fine pitch PBGA and 3D-stacked die CSP packages.
When evaluated on these packages,the compound provided very good wire sweep performance. It also has the ability for
lead free solder re-flow at 260oC after JEDEC Level 3 pre-conditioning. In order to minimize wire sweep,a new resinhardener-
catalyst system was developed. The optimized combination of resin system provides extremely low viscosity and
long gel time. X-ray results showed that wire sweep less than 2% can be consistently achieved on PBGA and stacked die
packages using 0.8mil wire. The low moisture absorption of the new epoxy mold compound minimized delamination
between mold compound and die at lead free soldering parameters.

As the need for higher performance,higher I/O count packaging solutions at lower costs continues to grow,opportunities
exist to support these applications with higher performance wire bonded packages,as an alternative to some of the more
expensive FlipChip solutions.
This paper details the unique design layout and engineering development methodologies that were used to produce a family
of organic wire bonded BGA packages. This family of packages utilizes a ‘Stripline’ cross-sectional structure in contrast to
the more commonly used ‘Microstrip’ structure for electrical enhancement. This enhancement is combined with the package
designed to support both ‘Single ended’ and ‘Differential’ I/O’s as well as providing support for multiple I/O voltages. In
supporting the need for increased power dissipation,built in heat spreaders as well as optimized thermal via and solderball
layouts have been designed into the package.
The packages are able to support a high density of I/O’s per unit area of the die,by combining an optimal layout of multiple
rows of bonding pads on the die with a package layout that promotes the electrical enhancement features. Our modeling and
characterization of this family of packages conclude it meets the high performance requirements needed of the next
generation electronic packages.

The world-wide movement to phase out lead from electronic products presents many challenges for companies throughout
the electronics supply chain. The University of Massachusetts Lowell has brought together nine Massachusetts firms to
collaborate on the manufacture and testing of lead-free printed wiring boards (PWBs). The results of the first set of
experiments,published in 2001,showed that zero-defect soldering is achievable with lead-free materials. Following thermal
cycling,the PWBs were visually inspected and the leads were pull tested for reliability analysis. They compared favorably to
a baseline of lead soldered PWBs
A follow-on design of experiments was created in 2002 and a second set of test PWBs was made and tested in 2003. Several
lead free solder pastes (3) based on Sn/Ag/Cu were used with a variety of surface finishes (5),comp onent types (4)
component finishes (2) and reflowed using either air or nitrogen. Visual inspection and pull testing has been completed and
published in APEX,SMTI and IEEE conferences. This paper summarizes the effort and conclusions to date and discusses the
methodology of the pull-testing phase after thermal cycling.

The continued functional densification and integration in networking products is driving the need to study large form factor
printed circuit boards that use high I/O packages (either ceramics column grid arrays,CCGA,or plastic ball grid array,
PBGA). As of today,there has been limited work on understanding the impact of lead-free soldering on these large and
complex assemblies. This paper will look at larger packages (up to 52.5mm square with 2577 I/O) in combination with
lead-free soldering. Assembly processes such as solder paste printing and reflow soldering will be studied and the results
presented. The rework of these component types will be evaluated and the key issues for developing a successful rework
process will be discussed.

Movements to lead-free assembly are being influenced by legislative and market requirements. Specifically Europe has
passed legislation requiring the removal of lead from electronics assembly by 2006. Also,the perceived marketing advantage
of a “green product” is beginning to be accepted. Though development work for lead-free components is increasing,work on
lead-free components with higher I/0 has been fairly limited at this time.
The present work describes the evaluation of a 780 I/O lead-free Flip chip BGA component in terms of assembly below
260°C peak reflow temperature. FCBGA components were assembled at peak reflow temperatures of 225°C,235°C,245°C,
reflow environments of air and nitrogen,and rework with peak reflow temperature 230 to 235°C with a novel rework nozzle.
Solder joint formations from the different reflow processes were inspected using visual analysis,XRAY analysis,and
physical cross sections. Each inspection showed good solder joints of all components mounted at the different peak reflow
temperatures and environments.
Reliability of the mounted components was then tested by temperature cycling from 0-100°C. All components mounted in the
different peak reflow temperatures and environments were stressed with the bulk of the stressed devices from reflow peak
temperature of 235°C in nitrogen environment. All mounted components survived greater than 3500 cycles.

For SnAgCu solders,the voiding rate at microvia was studied with the use of simulated microvia,and was the lowest with
95.5Sn3.8Ag0.7Cu and 95.5Sn3.5Ag1Cu. The voiding rate increased with decreasing Ag content from 3.5Ag,mainly due to
an increasing surface tension. Voiding at microvia was governed by via filling and exclusion of fluxe s. The voiding rate
decreased with decreasing surface tension and increasing wetting force which in turn was dictated by the solder wetting or
spreading. Both low surface tension and great solder wetting prevented the flux from being entrapped within microvia. A fast
wetting speed might also facilitate reducing voiding. However,this factor is considered not as important as the final solder
coverage area.

This paper presents a quantitative analysis of solder joint reliability data for lead-free Sn-Ag-Cu (SAC) and mixed assembly
(SnPb + SAC) circuit boards based on an extensive,but non-exhaustive,collection of thermal cycling test results. The
assembled database covers life test results under multiple test conditions and for a variety of components: conventional SMT
(LCCCs,resistors),Ball Grid Arrays,Chip Scale Packages (CSPs),wafer-level CSPs,and flip-chip assemblies with and
without underfill. First-order life correlations are developed for SAC assemblies under thermal cycling conditions. The
results of this analysis are put in perspective with the correlation of life test results for SnPb control assemblies. Fatigue life
correlations show different slopes for SAC versus SnPb assemblies,suggesting opposite reliability trends under low or high
stress conditions. The paper also presents an analysis of the effect of Pb contamination and board finish on lead-free solder
joint reliability. Last,test data are presented to compare the life of mixed solder assemblies to that of standard SnPb
assemblies for a wide variety of area-array components. The trend analysis compares the life of area-array assemblies with:
1) SAC balls and SAC or SnPb paste; 2) SnPb balls assembled with SAC or SnPb paste.