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While silicon density doubles approximately every 18 months,following Moore’s law,PWB electrical technology advances much more slowly,Up until now trace impedance has been a sufficient high speed electrical specification for PWB traces. PWB manufacturers utilize time domain reflectometry (TDR) to measure trace impedance. The original IPC specification for TDR was written 20 years ago by this author.
Emitter Coupled Logic (ECL) logic drove need for controlled impedance early in the seventies,and considerations of topology and reflections have for some time been the main task for signal integrity engineering. Inevitably,the speed march has pushed gigahertz signaling onto the PWB,which presents new design challenges. At GHz frequencies,for instance,trace loss is actually more important than impedance. New materials and processes for RoHS could affect board loss characteristics.
Traditional loss measurements are done using vector network analyzers (VNA) which are costly and not well suited for a PWB manufacturing operation. A new IPC committee,D24a,has been tasked to develop a low cost TDR/TDT loss measurement method that can utilize pre-existing PWB equipment. The committee’s objectives are to develop a low-cost but accurate loss measurement method which empowers PWB manufactures to manage development of low-loss materials and manufacturing methods.
This paper will detail how a single TDR/TDT pulse energy value can be used as a loss specification. It will be shown how this single value method is as serviceable as a VNA measurement,while doing away with the exacting procedures required for the VNA approach.

This paper presents the qualification of a new,very thin,printed circuit board (“PCB”) dielectric substrate (“core”) to meet Teradyne’s performance and reliability design goals for a power supply (“PS”) printed circuit board.
The challenges included lower noise margin and higher current carrying capacity. These requirements needed to be met while reducing total product cost and improving system reliability. Newly available copper clad polyimide cores,if they were reliable,could provide a solution to achieving the design goals.
This paper provides details on: A) the design requirements and achievements; B) the core used,a copper-clad 25 micron [0.001"] polyimide film; C) an overview of the performance and reliability testing and results; and D) a quick look ahead at next generation even thinner cores for low inductance and electromagnetic interference (“EMI”) reduction.

Lead-free soldering is expected to become the new standard in the future. Different legislations or draft directives target the restriction or the ban of the use of lead in the world. As an example,the European Union adopted the Restriction of Hazardous Substances (RoHS) Directive in January 2003. It will come into effect on July 1,2006. Most of the lead-free solder alloys melt at higher temperatures than that of the eutectic SnPb solder. The change to higher temperature solder alloys will directly affect the temperature profiles for reflow soldering,wave soldering,rework and repair. Typical lead-free reflow profiles will reach peak temperature of 245°C to 265°C for up to a minute. De-soldering,rework and repair will reach peak temperature above 300°C for a few seconds. In parallel,the complexity of the boards is increasing,leading to thicker multilayer structures. Laminates will thus be submitted to higher temperature for longer time through multiple reflow cycles. It is critical to understand how these new technical requirements will have an impact on the thermal resistance of electrical laminates.
This paper aims to provide correlations between different techniques used to characterize the thermal stability of electrical laminates suitable for lead-free soldering.
• Thermo-Gravimetry Analysis (TGA) was used to measure the degradation temperature (Td) and the time to degradation at a given temperature (D-260,D-288,D-300);
• Thermo-Mechanical Analysis (TMA) was used to measure the time to delamination at a given temperature (T-260,T-288,T-300),the number of temperature cycles before delamination (Nd),and the coefficient of thermal expansion along the z-axis (CTE);
• Differential Scanning Calorimetry (DSC) was used to measure the glass transition temperature (Tg).
The thermal stability data of various epoxy systems will be described and correlated to specific applications needs. Various examples of epoxy systems will be chosen within the portfolio of The Dow Chemical Company.
Results suggest that conventional FR-4 resins might still be suitable for standard FR-4 applications that need only a few lead-free reflow cycles. When the number of cycles increases,enhanced resin systems must be considered to avoid in-process failure. Highly thermo-resistant products are suitable for complex multilayer build-up or for applications targeting high in-use temperature. In addition to thermal stability,other key laminate parameters for board reliability are adhesion and toughness.

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Embedded passive components are resistors,capacitors and inductors buried within a multilayer PCB. Embedded components pass standard reliability test methods,however,the higher temperatures required for lead-free solders increase the physical stress in the board. Component failures,although rare,are typically caused by high z-axis expansion,
lifted pads or innerlayer delamination that cracks and/or opens the embedded component.
High performance laminates designed for lead-free assembly offer a higher Tg and decomposition temperature and a lower CTE but bond strengths are lower than a corresponding FR-4 substrate. Metallic embedded components can withstand higher temperatures than organic substrates,however when the PCB is tested to failure by multiple solder shocks,the embedded component layer fails preferentially due to the lower bond strength.
A Design of Experiments for a PCB with embedded passives and lead-free assembled SMTs showed that laminates with light weight glass and high resin content giving the best results (no delamination after multiple thermal excursions). The conclusion is that embedded passives in multilayer PCBs built with high performance laminates using improved copper topographies,high resin content and light weight glass constructions are reliable for lead-free assembly.

Over the past six years Motorola has shipped over 47 million phones incorporating Embedded Passives (EP) technology. The EP modules shipped in phones have included small modules such as voltage controlled oscillators as well as large modules comprising full phone functionality. Driving the creation of a supply chain—from materials supplier through board fabricator—was also required in order to execute the transformation of embedded passives from R&D curiosity to reality in products. Every implementation of EP has maintained system cost parity or reduced system cost while benefiting from size and routing complexity reduction. This paper briefly reviews the commercialized portfolio of embedded resistor,capacitor,and inductor technologies,and uses several case studies to highlight the lessons learned.

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The number of applications using Embedded capacitor technology on Printed Wiring Boards (PWBs) is increasing. One of the increasing applications using embedded capacitor is high-speed digital application and another is module for hand held devices.
For high-speed applications,design of Power Distribution System (PDS) is becoming challenging and solution for EMI is becoming more difficult. Traditional method to cope with these challenges was to use discrete capacitor components by optimizing component type,amount and location. As LSI technology scales to faster transistors and lower voltage,this traditional method is becoming ineffective,inefficient and costly. Embedded Capacitor technology has proven to be effective to overcome these issues by contributing to provide low impedance PDS and reduce EMI. In this paper,we have studied effectiveness of Embedded Capacitor using commercially available simulation software.
For module for hand held devices,the demand for higher HDI is endless. One of solution for higher HDI is to embed capacitor function inside PWB. Although there are various embedded capacitor materials proposed,the challenge still lies in the PWB fabrication to form uniform and reliable capacitor cost effectively. In this paper,we propose practical method of forming embedded capacitor and discuss what can affect tolerance of capacitance value.

This paper is the second concerning the use of existing electrical test equipment being programmed to first measure the values of plated additive resistors manufactured on circuit board inner layers. Next,this value information is programmed into the software of a laser routinely used to drill microvias for circuit boards. A computer routine calculates the amount of the resistor that needs to be removed to adjust each resistor to the required design value. The trimming is then conducted on the actual inner layer.
Advantages of this technology include eliminating the manufacture of probe cards for each new circuit design,and utilizing existing machines for this new technology task. While accuracy of trim with this “off-line” machine may not be quite as precise as active trimming with probe cards,the accuracy is sufficient for many of the 5-10% resistor values needed for such design applications as digital signal termination. Plated additive resistors,with their uniform thickness across each resistor,are particularly easy for this technology combination to trim.