By using two existing pieces of common printed wiring board manufacturing equipment,embedded resistor manufacturers
can obtain laser trim results similar to the trimming obtained using a specialized probe card based laser trimmer. Existing
electrical test equipment can be programmed to first measure the values of plated additive resistors manufactured on circuit
board inner layers. Next,this value information is programmed into the software of a laser routinely used to drill microvias
for circuit boards. A computer routine calculates the amount of the resistor that needs to be removed to adjust each resistor to
the required design value. This trimming is then conducted on the actual inner layer.
Advantages of this technology include eliminating the manufacture of probe cards for each new circuit design,and utilizing
existing machines for this new technology task. While accuracy of trim with this “off line” machine may not be quite as
precise as active trimming with probe cards,the accuracy is sufficient for many of the 5-10% resistor values needed for such
design applications as digital signal termination. Plated additive resistors,with their uniform thickness across each resistor,
are particularly easy for this technology combination to trim.

We have previously published our work on developing thin substrates for use as embedded capacitor layers. Both unfilled
and filled materials were characterized in regards to performance,reliability and manufacturability. It was demonstrated that
higher capacitance density came at the expense of ease of processing.1 A new substrate was developed to address this issue.
As previously shown,high speed digital circuits benefit primarily from the capacitive layers being as thin as possible. For
mobile electronics,however,they want the highest capacitance density so they can remove the most discrete capacitors. With
both these markets in mind,a thin substrate with higher Dk than unfilled systems was developed. A major design objective
was to be able to etch both sides of the substrate at the same time (like traditional power/ground layers).
We will discuss the experiences of PWB shops in processing the material and review the results of the various reliability
studies. Also,test vehicles have been processed for testing at high frequencies to compare against the other capacitive
materials. It will be demonstrated that this new substrate has excellent electrical properties (such as a DK of 10 and the ability
to pass 500 volt High-Pot) while being able to be readily manufactured using typical inner-layer processing.
In addition we have developed a method,which utilizes our highest Dk material,which is compatible with HDI processing.
This process can be used to embed capacitance within an organic chip package.

The miniaturization of the electronics continues and requires the utilization of inner space of a PCB for component
placement. The embedding of the passive components inside the PCB has already been used in the industry. To meet the
requirement of the marketplace the new technologies like embedded actives Integrated Module Board (IMB) has been
developed. With traditional technologies it has become more difficult to increase the packaging density. In the Integrated
Module Board technology active components are embedded inside a printed circuit board (PCB) or other organic substrate.
The IMB process combines PCB manufacturing,component packaging and component assembly into a single manufacturing
process flow. The embedded passive technology and IMB technology enables high interconnection density with good
reliability.
The integration of components into the PCB level makes the manufacturing of the PCB challenging. In this paper an update
of embedded passive technology will be presented together with an overview of IMB technology,its technological capability
and electrical performance.

The current worldwide market for printed circuit boards is approximately $40 billion,with the multi-layer printed circuit
boards (MLB) comprising approximately 40% of the market. One of the most perplexing processing problems is poor
registration in multi-layer lay-ups. This leads to hundreds of millions of dollars in scrap and lost productivity,and
compromises performance in high-end applications. Significant progress has been made over the years to identify the critical
components responsible for improved reproducibility and reliability. However,as pitch (conductor spacing) becomes finer;
the registration problems of multi-layer board fabrication become more severe. Better analytical tools are needed to meet this
new challenge.

Interest in the adhesive strength of PCBs has recently come to the forefront of the industry. This has been driven by the
advent of lead free soldering processes that severely stress the mechanical properties of the board. For sometime,the
accepted test method for measuring adhesion in the PCB industry has been the widely used peel strength test. At the same
time,it has been common knowledge within the industry that this technique has been less than adequate in guarding against
delamination failures during reflow and wave soldering. In recognition of this deficiency,a new test was recently introduced
and the test method is now a part of IPC 650; the so called “T260 Method” in which a thermal event is imposed that causes a
delamination of the test specimen.
This paper presents a statistical comparison of the two test methods. The correlation is found to be very poor indicating the
failure mechanisms measured by the two tests are structurally dissimilar. An analysis is then carried out to mathematically
define the stress fields created by the two tests. As suspected,the stress fields are significantly different. Finally,these two
tests are used to compare the strength of two different copper adhesion promotion chemistries,the Black Oxide coating and
an Alternative coating. Most empirical observations have found that the performance of the coatings is equivalent; however,
only the T260 test agrees with this observation.

The emerging technology known as ‘flipchips’ is poised to take over the world of the portable device. In an age when
more and more power and functionality is being offered in ever smaller packages,the flipchip will become mainstream in
delivering the promise of “Information at Your Fingertips,Anytime,Anywhere”.
Flipchip technology places a specially prepared silicon chip onto a substrate for connection to other chips and to the
outside world. Also known as Direct Chip Attach,it uses no traditional packaging,no bond wires,has no lead frame,and
has a number of significant advantages and disadvantages compared to current mainstream technology.

New Chip Packages for advanced electronics are striving for higher density of the printed wiring boards. However,in the
supply chain,the PWB fabricator is often the last link that will learn what is needed in terms of packaging density,hole size,
line width and space,surface finish and dielectric material requirements.
At the Wireless Terminal Business Unit of Texas Instruments in Denmark,new packaging technology combined with new
chip functions are tested in reference designs. This takes place one to three years before the products enter the market in
larger quantities. At the early product development only small number of PWBs have to be made to prove that the
functionality of the hardware is working and to provide software engineers with "Reference Design" printed circuit boards
that will enable software engineers to develop the software for new mobile phone applications.
PWB fabricators that are involved in the early product development have to manufacture PWBs using new fabrication
technologies and often new materials as well. The involvement in this advanced technology allows the PWB fabricators to
have a one to two years time span to get the technologies and materials integrated in production for large quantities. The
reality often demonstrates that proto series are made at companies that do not manufacture volume series at a later stage.
Making fast turn around in small series block relatively high capacity in a volume factory and is often avoided unless volume
orders are attached.
Based on the past history,it will be explained how difficult it was to have the total supply chain lined up to meet the PWB
fabrication technology to manufacturing PWBs for latest chip packages and to be able to source high quality PWBs at
acceptable delivery time and cost.

Fluctuating demand for electronic equipment has led to repetitive “boom and bust” business cycles throughout the electronics
“food chain.” Double ordering,inventory building and component outages in expansionary times are followed by
recessionary periods where demand shrinks,excess inventory must be consumed and severe downward pricing and margin
pressures are the norm. Raw material and process equipment suppliers see amplified demand in growth periods and severe
draughts during recessions because of inventory building and reductions at each level of the supply chain.
This paper compares the relative growth (and time shifts) at each level of the supply chain at various periods in the business
cycle. Items studied include:
- Economic indicators
- Electronic equipment orders,shipments and inventories by end market
- Semiconductors
- Connectors
- Printed circuit boards
- EMS demand
- Process consumables and equipment used to manufacture and test “members” of the electronics food chain.
Global and N. American data sources are identified and utilized including process consumables from the IPC statistical
surveys.
These data sources can be used to understand and predict the timing and magnitude of forthcoming downturns and recoveries
in the electronic industry business cycle. The methodology discussed applies to the entire “food chain” – electronic
equipment manufacturers,EMS companies,PCB and other component manufacturers and suppliers of materials and
equipment to these companies.

Information Technology has come a long way from the humble payroll accounting system to integrated suite of business
applications,ostensibly to assist corporations to manage their businesses more effectively. IT disciplines in some
corporations even have a Chief Information Officer at the executive VP level with considerable clout and influence in
orchestrating the pervasiveness of IT at the all levels of the corporation. This has fueled a great appetite of expectations from
major system houses to develop and deploy the IT/ information thinking notably at the middle and top level of management.
There is ample evidence that moneys and efforts have been deployed,however the results are mixed. This paper discusses the
challenge of deploying IT and systems thinking in the corporate suite: a collection of tactical and strategic information
displayed about the performance of the business not very different from the information displayed to a driver in the
dashboard of an automobile.

As PCB computing bus frequencies climb above 1GHz,measurement of the high-frequency properties of PCB materials
becomes critical for design modeling. Understanding these properties and their dependence on temperature and humidity will
enable manufacturers to formulate new materials that will be less subject to variation. This paper will introduce a method of
measurement of loss tangent and relative permittivity of solder mask from 1.2 to 10.2 GHz and show the sensitivity of these
properties to variability of temperature and humidity. The solder mask is coated on one side of a Corning® 7980 high-purity
fused silica (HPFS) disc. This disc is inserted in a split-post dielectric resonator (SPDR). The resonance of the SPDR plus
uncoated disc is compared to the resonance of the SPDR plus coated disc to calculate the loss tangent and relative
permittivity of solder mask. This coated-disc technique has been used to determine the properties of other microwave
materials.