The trend towards tighter pitch,smaller features,and shrinking pad sizes have put a strain on the standard photolithographic
processes for soldermask patterning on substrate packaging and rigid Printed Circuit Boards (PCB). These constraints have
limited the ability of the package/board designer to shrink features and have resulted in yield losses by the fabricators. To date,
the answer to this situation has been to re-capitalize with expensive Laser Direct Imaging (LDI) systems or modified
semiconductor step and repeat equipment. This paper discusses direct laser ablation of soldermask as an alternative technology
to enable fabricators to achieve very tight soldermask feature control.
Presented in this paper is the process and performance evaluation of the direct laser ablation process on soldermask for very fine
pitch package placement on printed circuit boards. Results of solder adhesion,pre-surface finish pad morphology,and solder
joint reliability to shock,bend,and thermal cycling are reviewed across design and process parameters. The evaluation looked
at fabrication process variations across different soldermask types and soldermask thicknesses. Design implications between
soldermask defined pads,metal defined pads and via in pad when used with soldermask direct laser ablation were also
investigated.

Polymer-ceramic nanocomposites based on new concepts were developed for embedded capacitor applications. The dielectric
constant was above 80 at 1 MHz and the specific capacitance was successfully achieved 8 nF/cm2. By use of this
nanocomposites,multilayer printed wiring boards with embedded passive components were fabricated for prototypes. The
following technologies would be reported in this conference.
Firstly,based on the investigation of barium titanate (BaTiO3) crystallites,various particles with the sizes from 17 nm to 100
nm were prepared by the 2-step thermal decomposition method from barium titanyl oxalate (BaTiO(C2O4)2 4H2O). It was
clarified that BaTiO3 particles with a size of around 70 nm exhibited a maximum dielectric constant of over 15,000.
Secondary,the BaTiO3 surface modification based on a new concept was applied to improve the affinity between BaTiO3
particles and polymer matrix. Thirdly,the blend polymer of an aromatic polyamide (PA) and an aromatic bismaleimide (BMI)
was employed as the matrix from a view-point of both the processabilty during fabricating the substrates with embedded
passive components and the thermal stability during assembling LSI chips. Finally,these technologies were combined and
optimized for embedded capacitor materials.

Nanotechnology is receiving a lot of attention from companies,universities and governments. The US $3.8million National
Nanotechnology Initiative is matched by initiatives in Europe and Asia. But what does it mean for existing businesses and
new businesses in the electronics market. Is it a real tool for today or are the applications way out in the future? Will it be
economic or outrageously costly?
In reality,nanotechnology is like a toolkit for the electronics industry; it gives us tools that allow us to make nanomaterials
with special properties modified by ultra-fine particle size,crystallinity,structure or surfaces. These will become
commercially important when they give a cost and performance advantage over existing products or allow us to create new
products.
The presentation will outline areas in nanotechnology with specific impact on semiconductors,passive components,display
materials,packaging and interconnection.

Design for test rules (DFT) for in circuit test (ICT) test pads are well known and have served the industry well for nearly two
decades. However,increasing PCB densities continually put pressure on board designers to eliminate ICT testpads.
Furthermore,recent technical advances in operational board speeds are leading some designers to believe that ICT test pads
cannot be added in the high-speed sectors of boards soon to be designed. Since the effectiveness of ICT is directly related to
test pad access,some have questioned the long-term viability of ICT in this high density/high speed PCB environment.
Parker has introduced a new ICT probe technique in 2004 to address these issues.1 We’ve been calling them “bead probes”.
Parker shows that this new technique will not degrade the high-speed circuit performance of tomorrow’s gigabit logic boards.
He also presents test results showing that this new technique can be used with typical PCB assembly processes and ICT
fixtures with similar electrical performance and reliability to current ICT probing techniques.
This paper will continue that discussion and further demonstrate how these non-traditional pads have little impact on layout
for test pad placement using results from a real PCB design process. It will discuss DFT guidelines for “bead probes” and
discuss possible barriers to creating beads in an outsourced manufacturing environment. Finally,now that ICT access to highspeed
sectors on PCBs will be available,a survey of viable ICT test techniques will be presented.

The design and evaluation of a wide bandwidth (3 dB attenuation bandwidth > 20 GHz),50 S,coaxial probe for the
electrical characterization of printed wiring board (PWB) transmission lines is described. The probe made thousands of
repeated contacts,using spring-loaded interconnects,without affecting probe performance. The probe contains an internal
mechanism for dissipating static charge on the signal line of the PWB transmission line and is long enough (approximately
10 cm) to act as a transfer standard for characteristic impedance testing per the time -domain reflectometry test method
described in IPC TM 2.5.5.7.

In today’s complex manufacturing test environments,it is becoming increasingly difficult to detect and diagnose structural
faults within highly complex multi-layer PCB designs that offer extremely limited physical test access.
The widespread use of array style packaging i.e. BGA,CSP and FCA have resulted in significant limitations in physical test
access,reducing the effectiveness of conventional test methods such as in-circuit test in favor of other complimentary test
strategies. This is further complicated by the EU directive (WEEE and RoSH) that legislates that companies must adopt a
lead-free soldering process by 2006,which will have a significant impact on the effectiveness of physical contact probing
methodologies i.e. in-circuit test and flying probe testers.
This paper explores the utilization of boundary-scan as an alternative complimentary low-cost,high-performance but more
importantly a non-contact,fixture -less test methodology. It also examines the significant benefits offered by importing legacy
boundary-scan tests directly,without the need for redeveloping tests for execution on to a contract manufacturers preferred
test platform.

Small form factor and high density of printed circuit boards (PCB) have been already realized by flip chip (FC) bonding
technology. However,the requirement for finer pitch PCB is still increasing with shrinkage of die and wiring. Therefore,
conventional FC bonding technology will not provide sufficient capability or productivity to meet future demands.
The authors have focused on flip chip bonding method utilizing ultrasonic vibration. Flip chip modules using flexible printed
circuit (FPC) are strongly required for such as mobile phone applications. For that purpose,we investigated to assemble
semiconductor devices with FPCs applying this method,particularly for large size die with multiple pads. In this report,we
evaluated relationship between bonding parameters and reliability using several kinds of copper clad laminate (CCL) with
different plating conditions. We show the correlation between formation of microscopic metallic bond and actual chip on flex
(COF) module performance. As a result,we succeeded in realizing 35 micrometers pad pitch COF modules.

The comparison of the thermal pattern and the deformation pattern both are obtained on the surface of Printed Circuit Board
(PCB) was done to understand how both patterns correspond to each other. In the present study,both the FEMLAB simulator
and Thermography were employed for the study.
A Holographic Pattern Measuring System (HPMS) and an Interferometry Imaging System (IMS) were used. The test results
showed that both thermal pattern and deformation pattern were different from each other. We found that we could not deduce
the thermal deformed pattern on a PCB from its thermal pattern.

This paper describes part of a research effort currently under way in the field of print defect detection. The techniques
described have proven to be robust and particularly well suited for detecting troublesome bridge and bridge-like features that
span the gap between pads.

After the world electronic circuit industry finally turned out from the unprecedented recession,the business management of
today’s printed circuit industry may possibly have a chance to take a comfortable breather for a while. However,looking into
the trends and drivers of the industry,many people are still endeavoring to look for the next step in business development as
the competition environment is changing so rapidly. Today,China’s electronics market catches much attention for the
business people both in China and around the world. Driven by relocation,restructuring and supply chain management and
changes in China’s electronics manufacturing market and printed circuit supply,there are more features of China printed
circuit industry today,both with market opportunities as the industry is developing and with challenges which have to be
watched and turned into business development opportunities. Behind the growth of the China printed circuit market,there is
much more to improve and to collaborate.