Epoxy molding compounds are used extensively in the electronics industry to encapsulate surface mount Integrated Circuits
(ICs). The primary purpose of encapsulating the SMT package using these molding compounds is to protect them from
adverse conditions. Though the mechanical and electrical properties of epoxy make it suitable for electrical and electronic
applications,epoxy is not a hermetic encapsulant and will allow moisture to diffuse into the components. The absorbed
moisture affects the properties of the material especially when the components are reflowed and can lead to failures like pop
corning and package cracking. Moisture induced reflow failures due to pop corning and delamination in plastic encapsulated
SMT packages has been a significant issue in the assembly of PCB’s. The impending transition to Printed Circuit Board
(PCB) assembly involving more rigorous reflow conditions,accentuates the need for study on the integrity of such packages
during and after assembly. This research involves the study of moisture and reflow sensitive behavior of an array of plastic
encapsulated packages to assess their performance at both eutectic and lead free reflow conditions

Successful reflow soldering is a key to productivity and profitability,yet many assemblers may be using a nonoptimized
reflow profile.
Years ago,when IR ovens were the norm and solder pastes were relatively unsophisticated,initial reflow profiles were
developed (Figure 1). These profiles were called “ramp to dwell – ramp to peak.” Since then,IR technology has bowed to the
superior capabilities of convection technology,with its dramatically different heating mechanisms. Additionally,solder paste
formulation technology has evolved significantly in the same time.
Recent work by Lee1 indicates that these IR reflow profiles are not optimum for convection ovens and modern solder pastes.
Through the analysis of defect mechanisms,his work reveals that a gentle ramp to about 175°C,and a very gradual rise
above liquidus,followed by a ramp to a peak temperature of 215°C will result in the highest yields. An example of the “Lee
Profile” is shown in Figure 2. When one considers that almost all ovens used in SMT assembly are convection ovens,this
distinction in reflow profiles is very significant.

When transitioning to lead-free reflow,consideration should be given to the additional costs of operation,above and beyond
material costs.1 Impacts to the overall reflow process should be carefully reviewed. Due to the higher operating temperatures
required for lead-free processing,and the suggested use of nitrogen,equipment cost of ownership could dramatically
increase.2
This paper evaluates power consumption rates for both lead-free and traditional leaded reflow processing along with
reviewing a unique,closed-loop nitrogen control design that automatically varies the flow of nitrogen to maintain ppm levels
and reduces nitrogen flow during idle states. Data obtained under loaded/unloaded conditions will be presented in relation to
varying power consumption results. A cost of ownership model is also used to predict additional expenses over time,along
with suggestions on equipment feature/option considerations for lead-free reflow processing.

The impedance and electrical property variation resulting from spatial patterns in woven glass reinforced laminate materials
are greatly impacting high speed interconnect designs. As the transfer rates of PCB interconnects increase,the allowable
timing tolerance between different nets on the PCB is shrinking to a point where the resulting local variations in dielectric
constant due to variations in woven fabric density are becoming a limiting factor. These local variations place limits on
transfer rates of PCB interconnects and are shown to be a constituent of impedance control within a PCB layer. The spatial
properties are shown to be dependent on the glass cloth and resin system selection,design layout rules,and pcb stack-up
parameters. This paper details the electrical property variations that exist in common laminate material and glass styles and
discusses the impact on IO bus modeling and lay-out design.

This paper will discuss the two primary transmission components that concern designers today. These components affect the
signal integrity of all high-speed transmissions in printed circuit boards (PCBs).
The dissipation factor (Df) is a laminate material parameter that determines the losses assigned to the laminate surrounding
the transmission line. For a good dielectric,the conductivity,which determines Df,should approach zero. Signal processing
at high speed requires that the dielectric constant (Dk) that is perceived static and the effective dielectric constant (Er') that is
perceived active,be measured so that the designers have an accurate model to predict delays and impedances. For these highspeed
signals,the delay (phase or propagation) is critical to the success of any high-speed transmission path. Delays through
the transmission line can affect skew,influence noise immunity and may reduce eye widths. An accurately measured Er'
obtained from signal delay is needed to ensure that no impedance mismatches associated with laminates are found along the
transmission path.

Efforts to reduce high frequency signal losses associated with dielectric materials have driven development and
commercialization of more cost effective low loss laminate materials. These developments have been facilitated by the use of
a variety of standardized dielectric test methods.
As dielectric losses are reduced,the relative contribution of conductor materials to overall loss increases. In order to better
understand the implications of conductor material and surface finish choices,efforts have been made to quantify the impacts
of these factors on loss.
While conductor material and surface finish influences may be directly measured using printed wiring board test structures,
interpretation of the results are complicated by the influence of both the laminate material and the particular geometry
selected for the test structure (microstrip versus stripline versus differential pair). The results of such measurements
accurately reflect the specific test geometry examined,but are difficult to extrapolate to different systems.
An alternative test approach has been identified which provides a measure of conductor performance,decoupled from both
system geometry and the influence of laminate material.
The basic test method described in IPC TM-650 2.5.5.5.1. (Stripline Test for Complex Relative Permittivity of Circuit Board
Materials to 14 GHz) has been modified by comparing the results obtained using ideal smooth copper conductors and with
those obtained with samples of alternative conductor materials,while maintaining a constant dielectric material. Changes in
the resonator loss factor between the two tests allow calculation of the relative performance of the alternative material versus
the ideal conductor.
Using this test method,the performance of a number of surface finishes,PWB foil treatments and inner-layer adhesionpromotion
processes relative to a control smooth copper surface are reported.

A common industry practice is to confirm the characteristic impedance of critical PCB traces meet specified performance
tolerances before any components are attached. A popular technique is to use a time domain reflectometery (TDR) to derive
the characteristic impedance from reflections of a pulse injected into the designated “test” trace. One problem with the TDR
method is that interconnect anomalies located closer to the TDR launch location can impact the “apparent” impedance of
interconnect geometries following the anomaly. For example,through and stub via effects,trombone delay lines,and skin
depth losses can easily cause the computed TDR impedance to falsely indicate an out-of-tolerance condition,when in fact the
PCB is properly constructed. This paper describes what measures can be taken during the PCB layout to ensure that
subsequent TDR measurements of critical impedance-controlled traces will accurately represent the true characteristic
impedance.

This paper will discuss how R/flex® 3000 LCP materials from Rogers Corporation are "pushing the envelope" for high -
frequency & flex designs by examining:
1. How the material set has now been characterized out to 110 GHz,and why this can open the door for "ground-up”
liquid crystalline polymer (LCP) designs-ins.
2. What combinations of very thin film laminates and bond plys are now available,and how their electricals are
virtually unaffected by environmental conditions.
3. Which foils are available on the laminates with suggestions on their application,including test results with resistive
foils.
4. Where we see opportunities for producing tomorrow's circuit designs today.

Numerous technical articles have dealt with machine parameters,and their effect on wave soldering of Printed Circuit Boards
in the range of 40-93 mils and the typical 6 to 8 layers. This research concentrates on identifying the key process parameters
that affect wave soldering with 63Sn/37Pb solder on a 15 layer (9 signals and 6 power and grounds) board that is 104 mils
thick. A detailed Designed Experiment was developed and executed in multiple stages to identify the full impact of all the
factors considered. Key response variables that would impact yield and reliability of the product were considered. The results
were analyzed using the ANalysis Of VAriance or ANOVA approach. The aim of the research effort was to find a global
solution that would work well for 60 to 200 mils thick boards. The study was also aimed at finding more specific solutions
for other products based on board thickness. To date,this process had been successfully implemented on 135 mil thick 26
layer boards and 187 mil thick 16 layer boards.

Surface mount assembly has dominated its through-hole predecessor since the early 1990s. The higher density and lower
ultimate cost of SMT makes it a preferred assembly technology. However,the mechanical strength of through-hole
connections continues to make through-hole the technology of choice in assembling connectors. This presentation will
describe the primary methods currently used for through-hole connector assembly: 1) selective wave solder,2) pin-in-paste
(PIP),1 reflow,3) hand soldering and 4) solder preforms. We will show how solder preforms are an excellent alternative when
PIP provides insufficient solder.
The wave solder method requires specialized equipment and processes to solder connectors. Pin-in-paste reflow evolved as a
way to accomplish through-hole assembly without additional equipment or process steps. In the PIP method,the additional
solder required to fill the though-hole barrel is deposited by overprinting the pad in the area of each connector pin,using
standard SMT equipment. During reflow,the solder wicks to each pin forming the solder fillet.
This paper explains why pin-through-paste reflow methods based on overprinting solder paste have become more challenging
due to an increasing use of Organic Solderability Preservative (OSP),fine-feature devices (e.g. fine pitch connectors) and
densely populated PCB layout designs that conflict with requirements for successful use of step-stencils. This paper also
shows an example where solder preforms were used to provide extra solder volume for each pin. This work demonstrates
how solder preforms provide a viable manufacturing solution to ensure complete through-hole solder joints.