Photochemical machining (PCM) is an excellent method for manufacturing both simple and complex parts in a wide range of
engineering materials. In the harsh economic climate facing manufacturing industry today,it is important to utilise costeffective
processes to produce high-quality parts rapidly for just-in-time delivery. This paper discusses the best methodologies to utilise PCM to its full extent as an extremely versatile process within the electronics,electrical and mechanical engineering disciplines.

Lead free soldering with no clean solder pastes represent nowadays the most common process in electronic assembly. A solder paste is usually considered as no-clean if it passes all IPC J-STD-004 corrosion tests: copper mirror,copper panel corrosion test,Surface Insulation Resistance (SIR) and Elecrochemical Migration (ECM). Other SIR and ECM tests are described in Bellcore GR-78-CORE and JIS Z3197 standards.
Although SIR and ECM tests are recognized by all standards authorities to evaluate the solder paste residue corrosivity after reflow,a more selective method,the Bono test,has been developed and implemented in some French companies as a qualification criterion. It has been proven that compared to common corrosion tests,the Bono test better differentiates the nature of solder paste residues.

Electrochemical migration (ECM) is the growth of conductive metal filaments on a printed circuit board (PCB) through an electrolyte solution under a DC voltage bias. ECM can cause a reduction in surface insulation resistance (SIR) between adjacent conductors,generate a path of leakage current,and lead to intermittent or catastrophic circuit failures.
Solder mask has been widely used on printed circuit boards to define wettable surfaces,reduce moisture access,control outer layer impedance,and improve corrosion resistance. The mechanical and thermal properties of solder mask have been widely reported,but systematic studies of their influence on ECM have been few. This paper presents the results of temperature-humidity-bias (THB) testing of more than 1000 hours duration at 40V,65°C,and 88% relative humidity for comparative evaluation of ECM on circuit boards with and without a solder mask. The boards were HASL finished and wave soldered using a no-clean,low solids flux. Besides primarily assessing the effects of using a solder mask on ECM,the effects of solder alloy composition (eutectic SnPb versus Sn-3.0Ag-0.5Cu) were also investigated. In situ monitoring of SIR was performed throughout these tests. Optical microscopy and scanning electron microscopy were employed to examine the correlation between the physical attributes of dendrites and the measured SIR,as well as to evaluate the effects of solder mask and solder alloy on ECM. Ion chromatography (IC) was conducted to measure contaminant levels on the surface of the PCBs. Elemental mapping by energy dispersive X-ray spectroscopy was employed to identify the migrating species and their distributions and morphologies within the dendrites. As expected,the use of a solder mask resulted in higher SIR,but a dramatic difference was observed in its effect on dendritic growth and characteristic life.

Many electronics manufacturers perform SIR testing to evaluate solder materials and sometimes the results they obtain differ
significantly from those stated by the solder material provider. The difference in the results is typically the result of SIR coupon preparation. This paper will discuss the issue of SIR coupon preparation,board cleaning techniques,and how board cleanliness directly affects SIR results.
We will also discuss the differences between two of the industry’s most common SIR specifications J-STD-004A and -004 B. The subjective nature of SIR testing on water washable/soluble materials will also be reviewed. In addition,testing for SIR
when the assembly process has multiple residue sources,such as paste,wave solder flux,rework flux,etc.,will be considered.

Using embedded structures in printed circuit boards,changes in moisture content have been monitored using route-impulse-energy measurement,capacitance measurement and weight gain. All three methods showed good correlation for different prepregs with similar structures.
Two designs of capacitor plate,a solid plate and a multi slotted plate,showed significantly larger percentage increases in capacitance values (10%) than the corresponding mass increases (0.35%) from moisture ingression effects. A good correlation was also obtained between the RIE measurement results and the board mass changes The RIE values showed significantly larger percentage increases (20%) than the corresponding mass increases (0.35%) over a similar timeframe.
Although some results indicated a slightly greater moisture take-up for the 2116 prepreg samples compared to the 7628 prepreg samples,the majority of measurements did not show significant performance differences between the two prepreg types.
Both the RIE measurement and capacitance methods show promise in evaluating the moisture content of printed circuit boards. Capacitance measurements using capacitors of a solid plate design,have the disadvantage of inhibiting the take up of moisture if the plates are near the surface of the PCB. RIE coupons have an aspect ratio which enables them to be relatively easily incorporated into the break-off panel that commonly occurs around the outside of many PCB designs during manufacture. Provided that similar coupons had been characterised in the dry condition previously,and that the PCB has the same build characteristics,both types of coupon could be interrogated immediately prior to assembly,to determine the current level of moisture content.

Moisture plays an important role in the integrity and reliability of printed circuit boards (PCBs). The presence of moisture in a PCB alters its thermo-mechanical properties,induces hygroscopic stress through differential swelling,reduces interfacial adhesion strength,induces corrosion,causes internal shorts through metal migration,and affects the performance of PCB. Past studies on thermal property measurements of PCB materials were conducted as per IPC test methods,including preconditioning of test samples. Some measurement results did not match the values quoted in manufacturers’ datasheets.
This experimental study examines the dependence of out-of-plane coefficient of thermal expansion and glass transition temperature on the moisture content in halogenated and halogen-free PCB materials. Furthermore,this study establishes the suitability of IPC-TM-650 preconditioning steps for thermal property measurements. Commercially available PCB materials from two manufacturers,including materials containing halogen-free and halogenated flame retardant,were tested in this study. One set of test coupons were preconditioned and tested per IPC-TM-650 2.4.24 (Glass Transition Temperature and Z-Axis Thermal Expansion by TMA) and IPC-TM-650 2.4.25 (Glass Transition Temperature and Cure Factor by DSC) test methods,and held as controls. Two additional sets were preconditioned at 105°C and,85°C and 85% RH for varying periods.
The results showed that glass transition temperature and thermal expansion coefficient are affected by both moisture and temperature. Tg decreased with increase in the moisture content in laminates,while it increased with an increase in the duration when exposed to thermal conditions. Moisture dominated the trends before laminate materials reached a moisture saturation point; while temperature dominated the trend post saturation point. Also,the results showed that there was no significant effect of moisture content on out-of-plane coefficient of thermal expansion values below and above Tg,while the values between 100ºC and the glass transition temperature were affected by moisture content,specifically in halogen-free materials.

Values for printed circuit board (PCB) laminate dielectric constant (Dk) and dissipation factor (Df) used in circuit design and signal integrity (SI) modeling are typically those presented on laminate maker datasheets. In most cases,these values are derived from measurements on samples which have not been exposed to thermal stresses representative of the printed circuit board (PCB) assembly process. This paper discusses the changes in Dk and Df values for a variety of laminate materials following simulated assembly thermal exposure of test vehicles to six SMT cycles at 260°C (Pb-free) or 225°C (SnPb eutectic). An additional concern arises around an effect of operating temperatures upon the effective Dk and Df of PCB materials. Due to thermal radiation from active IC devices,power supplies,etc.,the operating temperature of PCBs within a network equipment chassis is typically higher than the 23-25°C value at which Dk and Df are measured and reported. This paper also describes the changes in Dk and Df observed when the test samples were measured at temperatures of 50°C and 75°C.
1. Introduction and Background
2. Test Vehicle and Dk/Df Extraction Method
3. Assembly Thermal Simulation and Dk/Df Effects
4. Elevated Operating Temperature and Dk/Df Effects

The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free
technologies,generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball- Grid Array (BGA),Chip-Scale Package (CSP),or even a Package-On-Package (PoP) and is characterized as a process anomaly,where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section,it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources,such as solder ball oxidation,an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply,process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-inpillow defects. In addition,a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.

One of the most perplexing phenomena in the electronic manufacturing industry today is the defect called “head-in-pillow.”
Head-in-Pillow (HnP) defects occur on the blind solder joints of area array packages such as FBGAs,µBGAs and CSPs. Often these insufficient or intermittent solder joint defects go undetected during manufacturing despite inspection with conventional X-ray systems. They also are insidious reliability defects that often escape the normal testing procedures and fail at the end user site. The head-in-pillow defects typically occur at the corner pins and outer rows of packages and are associated with package warpage. There are new 3D imaging systems that can help detect this,but they rely on the operator to interpret the images. There are BGA video inspection systems that can view under most devices,depending on the standoff,but they are dependent on the access,viewing angle,and operator interpretation. These x-ray and video processes also are very slow and costly.
There are several factors that can contribute to the head-in-pillow phenomena including package co-planarity,package warpage,and assembly issues associated with solder paste characteristics and stencil printing. From a process standpoint,the cause of the head-in-pillow often is the result of the sum of all of the component and assembly process tolerances. This paper will discuss several contributing factors to the head-in-pillow defects and techniques to control them. It will include reviewing DOE for solder paste deposition of five different pastes,Shadow Moiré scans on several problematic devices,cross-section analysis of failed solder joints,and solder paste analysis of “head-in-pillow” pastes. The case studies presented show that process control can mitigate HnP defects but may not be successful for some severe examples of HnP defects.
This paper uses components from telecommunication product case studies to demonstrate the effects of different contributing factors and mitigation techniques for HnP defects. The case studies include reviewing solder paste printing modifications,solder paste DOE,Shadow Moiré scans on several problematic BGA packages,effectiveness of x-ray inspection,and crosssection analysis of failed HnP solder joints. Together,these case studies show that BGA package warpage is a major contributor,but HnP defects can occur when almost any of the assembly process parameters deviate from acceptable practices.

One of the effects of the ever increasing mountain of regulatory requirements and the globalization of markets is the need to
disseminate and collect information across the shop floor and the enterprise in either real or near real time. Companies are finding that a paper environment does not provide the nimbleness needed to execute today’s adaptive business models which are required in a rapidly changing economy.
Fortunately,a variety of process and information technologies have emerged and intersected to provide economical solutions for today’s process management and product traceability needs. Electronic process trees and instructions can be used as
collaborative information portals providing a wide range of capabilities. By strategically applying measured amounts of
technology to achieve the operational nimbleness needed,a company can stay relevant in what is becoming a rapid globalization of markets and regulations.