For many of the Pb-free solders required under the European RoHS directive,there is now sufficient information,primarily in the form of the results of accelerated thermal cycling of various levels of severity,to develop acceleration models for the creep-fatigue of these solders. In this paper the parameters for the SAC405/305,SAC205,SAC105 and SnAg to replace the parameters for eutectic SnPb in the well-established Engelmaier-Wild solder creep-fatigue model.

This presentation discusses critical material properties and test data that are often overlooked in the introduction of new lead-free solder alloys,but are critical to alloy comparison and the development of life predictive models and acceleration factors. Common gaps in property and test database are identified (e.g.,lack of creep data at low to medium stress and cold temperature,insufficient data under mildly accelerated test conditions). The importance of variations in temperature variables (cold and hot
temperatures) as well as dwell times is also discussed. Examples of thorough test conditions and test databases that have been used for the development of SAC305,SAC387/396 acceleration factors are presented. It is concluded that the “winning” alloys - i. e. alloys that end-users can work with – are those that are fully characterized in terms of metallurgy (including at interfaces) and mechanical / physical properties & their evolution; are robust enough under both thermal and mechanical loading conditions; and come with an extensive reliability test database and validated reliability models & acceleration factors.

Predicting the electrical performance of embedded capacitor PCB designs has been a major stumbling block for the technology. In particular,one of the key questions has been how quickly can charge be delivered to a device from the embedded capacitor. As pointed out in earlier papers (1,2) the major attenuator is the via connection between the ground plane and the embedded capacitor. These studies determined the performance when all of the charge is delivered through a single via. The index of performance for these investigations was the time constant associated with the capacitor’s discharge. It was found that a major reduction in inductance and hence the time constant could be achieved by minimizing the barrel length of the via; usually using blind vias.
The core of this paper examines other techniques for reducing the effective time constant and thereby improving performance. A potential strategy is using multiple vias between the device and the embedded capacitance. The analysis consists of developing a mathematical model of the circuit using the “lumped sum” approach commonly used in most electronic circuit analysis. With the model,we are able to predict the performance of the embedded sheet capacitor with multiple vias. Potential avenues for performance enhancement can then be identified.

Mixing PCB Design Layout units will compromise perfection every time. PCB Design perfection starts with building CAD
library parts and quickly moves to part placement,via fanout and trace routing challenges. Outputting data for machine
production can be extremely complex or very simple based on the PCB Design Layout units that were used throughout the
PCB design process. This paper reviews one of the single most important,but sometimes overlooked or taken for granted,
aspects of the electronics industry – The PCB Design Grid System

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The industry must address the technology gap between printed boards and semiconductor technology and how the semiconductor and IC packaging suppliers can combine resources in furnishing viable solutions. Although the development of fine-line substrates and assembly refinement has narrowed the gap somewhat,minimizing component outline,the array contact
format and reduced contact pitch is proving to be the most practical solution for uncased flip-chip and die-size package
applications.
This paper outlines the basic elements furnished in the newly released IPC-7094 ‘Design and Assembly Process Implementation for Flip-Chip and Die Size Components’ providing a comparison of existing and emerging wafer level and chip-size package methodologies. It will focus on the effect of PCB design and assembly of bare die or die-size components in an uncased or minimally cased format. The PCB design guidelines and assembly process variations furnished will provide useful and practical information to those who are considering the adoption of miniature bare die or die size array components.

Even though ink jet printed circuit has many advantages over typical subtractive PWB technology such as fewer processes,less waste and labor,it has some problems. A major problem is weak adhesion between circuit and substrate. The other problem with ink jetting conductor is poor line and edge quality. One of the most widely adapted solutions is the substrate surface treatments. The various treatment methods have been used to increase the affinity between substrateand ink. However,the resulting circuit quality was still not good enough to be compatible with conventional circuit. Therefore,printed electronics industry is looking for new method.
To meet this demand,a novel primer coating technology is developed. An aromatic primer was spin coated and dried on
either Fr-4 or PI substrate. The contact angle between nano silver ink and the coated surface has been increased more than three times to 50~70 degrees,resulting in quality ink jet printing. The line definition and edge quality of 100um/100um circuit after sintering was as good as those of conventional circuit. Fine pattern up to 25um/25um was possible using 10um nozzle. The adhesion by newly developed peel test method was 1~1.5 kgf/cm2,which is compatible with conventional PWB. The reliability of printed circuit was also good. The details of peel test method and reliability test results will be presented.

For several years,3D-integration approaches have been explored to keep pace with the continuous trends towards electronics
miniaturization and densification. Numerous technologies issued from various chip-,package- or board-level concepts can now be used and combined to achieve highly integrated “smart” systems. PCB embedding of passive and active devices is one of these advanced options with a strong potential : it enables a dramatic functionality increase while maintaining key PCB attributes of component and interconnects carrier. The presented paper will discuss some aspects of the PCB embedding technology developed in the frame of the HERMES project (High density integration by Embedding chips for Reduced size Modules and Electronic Systems). This European funded FP7 3 years research program targets to establish an industrial platform capable of producing PCBs with 2 layers of embedded components including large die sizes. The embedded PCBs manufactured will then be populated with external SMD components on both sides to constitute complex high-end integrated modules able to withstand conventional repair operations and ensuring a high reliability level. The work carried out will support the design and manufacturing of the various HERMES functional demonstrators for security,automotive and power module applications.

Manufacturers of electronic devices are always searching for new technologies that can improve processes,extend capabilities and lower costs. These drivers,along with the needs of new markets like Printed and Plastic Electronics,have brought processes like inkjet printing to the forefront. This paper explores the promise of what inkjet printing can bring to process simplification,cost reduction and improved capabilities. It also takes a critical look at the practical issues and concerns of this new technology.

Miniaturization and higher functionality in electronics packaging require the use of advanced packages and small components. This trend has translated into the use of new package types such as Quad Flat Pack – No Lead (QFP) (also referred to as Leadless Plastic Packages),increased use of chip scale packages as well as increased component density and tighter PCB layouts. Advanced package innovations and new flux types may compromise the validity of the R.O.S.E. cleanliness testing method. This paper researches the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies. The paper researches quality assurance and process control improvements needed to clean,extract,and measure the resistivity of solvent extract on today’s circuit assemblies.

Electronics manufacturing process engineers are faced with significant challenges when selecting a cleaning system as a
consequence of the wide ranges of cleaning processes and equipment. Currently available cleaning systems include aqueous
processes,semi-aqueous processes,monosolvent vapor degreasing and co-solvent vapor degreasing; while equipment options
include inline,batch,centrifugal and ultrasonic immersion. When matching the right process with the right equipment for a
specific application,many other factors must be considered including performance,capital expense,SHE (safety,health and
environmental) restrictions,throughput,available floor space,chemical compatibility and operating costs and maintenance
costs. An analysis of the total cost of ownership of a cleaning process is an important step in choosing the right process.
This analysis helps identify the lifetime costs of acquiring,maintaining and operating a process. This paper discusses the
factors,advantages and disadvantages that should be considered for each of the commonly used processes in the electronics
cleaning industry to help determine the total cost of ownership.