Microvia technology has many advantages: it requires a smaller designed area,which saves the board size and weight,using less space,allowing for a smaller PCB,which can results in lower costs,and the microvia allows for better performance due to a shorter pathway. The practical definition of microvia technology is “high density printed circuit substrates that employ via diameters of under 10 mils [250 microns] in diameter.” With all the benefits of the microvia,cleaning issues are often overlooked. Bare board manufacturers have been effective in cleaning the larger vias; however,is the cleaning process as effective on the smaller vias? Failure analysis data suggests that etch residues from the build process are being left in the microvias causing corrosion and electromigration failures. If residues are in vias under components,the risk of contamination related failures increases. Ion chromatography results repeatedly reveal the importance of board and component cleanliness as an indicator of product performance. Manufacturers have historically used a standard rinse process with heated de-ionized water after etch to remove process residues. This process has been effective with traditional larger vias,but may no longer be an effective process with microvia technology. This paper will explore multiple via sizes,different approaches to cleaning,and what data shows may be the most viable option for producing good performing product.

As people become more concerned about the global outbreaks of various strains of influenza,more precautions are being taken with respect to personal hygiene. A common precaution involves the use of hand sanitizer solutions or similar germicidal agents. For manufacturers of electronic assemblies,this may mean a potential transfer of these solutions/agents to the surface of the assemblies as a contaminant material. Similarly,many production employees in the electronics industry deal with harsh chemicals,which often remove hand oils resulting in chapped or dry skin. The use of hand lotions may or may not be allowed,depending on the manufacturer,with a similar concern regarding transfer of unknown chemicals to the assembly surface. This paper is an examination of some typical hand sanitizers and hand lotions and their impact on high reliability electronic hardware.

With increasing adoption of lead-free PWB surface finishes,along with increasing product deployments in more corrosive
environments,the electronics industry is observing increased occurrences of corrosion-induced product failures. Particularly,
creep corrosion on immersion silver has been observed to cause product failures after very short service periods in G2 and
worse environments,in some cases less than one year. In our previous work (APEX 2009) [1],we demonstrated that creep
corrosion of ImAg can be correlated to the presence of certain types of surface contamination (for instance residues left
behind by organic acid fluxes). In this work,creep corrosion observed on OSP finished circuit boards will be reported. The
effect of post-reflow cleaning process on creep corrosion will be discussed. A laboratory MFG test will also be discussed that
replicates field creep corrosion. Comparison of creep corrosion susceptibility between OSP and ImAg PWB surface finishes
will also be made.

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- Production Processes
- Manual Production Line (2000)
- Fully Automated System (today)
- Cell Interconnection
- Encapsulation Materials
- Encapsulation Process
- Influence of Temperature
- Encapsulation Equipment
- Edge Trimming Equipment
- Setting J-Box
- Framing Equipment
- Testing Equipment

Some ball grid array suppliers are migrating their sphere alloys from SAC305 (3% Ag) or SAC405 (4% Ag) to alloys with lower silver contents. There are numerous perceived reliability benefits to this move,but process compatibility and thermal fatigue reliability have yet to be fully demonstrated.
The current study has been undertaken to characterize the influence of alloy type and reflow parameters on low-silver SAC
spheres assembled with backward and forward compatible pastes and reflow profiles. This study combines low-silver sphere materials with tin-lead and lead-free SAC305 solder pastes under varied reflow conditions. Solder joint formation and reliability are assessed to provide a basis for developing practical reflow processing guidelines and to assist in solder joint reliability assessments.
This is the fifth report in a series being published as results become available,and presents the preliminary results of the thermal cycling portion of the test program. Thermal cycling conditions include both 0 to 100oC and -40 to 125oC,with 10 minute dwell times.

In this study,the reliabilities of low Ag SAC alloys doped with Mn or Ce (SACM or SACC) were evaluated under JEDEC drop,dynamic bending,thermal cycling,and cyclic bending test conditions against eutectic SnPb,SAC105,and SAC305 alloys. The Mn or Ce doped low cost SAC105 alloys achieved a higher drop test and dynamic bending test reliability than SAC105 and SAC305,and exceeded SnPb for some test conditions. More significantly,being a slightly doped SAC105,both SACM and SACC matched SAC305 in thermal cycling performance. In other words,the low cost SACM and SACC achieved a better drop test performance than the low Ag SAC alloys plus the desired thermal cycling reliability of high Ag
SAC alloys. The mechanism for high drop performance and high thermal cycling reliability can be attributed to a stabilized
microstructure,with uniform distribution of fine IMC paricles,presumably through the inclusion of Mn or Ce in the IMC. The cyclic bending results showed SAC305 being the best,and all lead-free alloys are equal or superior to SnPb. The reliability test results also showed that NiAu is a preferred surface finish for BGA packages over OSP.

Thermal cycling tests were conducted using two different ceramic ball grid array (CBGA) test vehicles having balls comprised of nine different Pb free solder alloys. The experiment was designed as a screening experiment to obtain data comparing thermal fatigue reliability of the various solder ball alloys. The test matrix was dominated by commercial SnAgCu (SAC) alloys but also included other high,low,and no-Ag alloys. The surface mount assembly was done with SAC305 (Sn3Ag0.5Cu) solder paste. The thermal cycling data,Weibull analyses,and metallographic failure analysis indicate that the best thermal fatigue performance was obtained with higher Ag alloys.

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Current carrying capacity in printed board design is technology dependent and an element of printed circuit board thermal
management. Conductor temperature rise as a function of current is dependent on the number of copper plane layers in the board,how the board is mounted,the ambient environment (air or vacuum),board thickness,board material,conductor thickness,and conductor width. How does one go about creating a single standard for something that is so variable dependent?
IPC2152,Standard for Determining Current-Carrying Capacity in Printed Board Design,begins with a baseline configuration that provides a conservative method for sizing conductors for carrying current in printed circuits. New charts included in IPC-2152 are based on tests conducted on traces in boards with no copper planes,suspended in still air as well as in vacuum. The baseline represents a defined board thickness,board material,conductor width and thickness,as well as variations with respect to those variables.
IPC-2152 is a technology enabler. Through the use of computer modeling and information within IPC-2152 and the Appendix,current carrying capacity design guidelines can be optimized for any variation in printed circuit technology. Until the publication of IPC-2152 this was not possible with the available public information.