Counterfeit electronic components are finding their way into today’s defense electronics. The problem gets even more complex when procuring DMS (diminishing manufacturing source) parts. This paper will provide a brief introduction to counterfeit prevention and detection standards,particularly as they relate to the Aerospace and Defense sector. An analysis of industry information on the types and nature of counterfeit components will be discussed in order to illustrate those most likely to be counterfeited,followed a specific case at a major defense contractor. The case involved two circuit card assemblies failing at test,whereby their root cause for failure was identified as “unable to write specific addresses at system speeds”. The error was traced to a 4MB SRAM received from an approved supplier. Fifteen other suspect parts were compared with one authentic part directly purchased from a supplier approved by the part manufacturer. Defects or anomalies were identified but not enough to unequivocally reject these parts as counterfeit as the defects could have also happened in the pre-tinning process,which is a program-specific requirement if the parts were stored for more than 3 years. Through the subsequent analysis,subtle differences between the authentic and suspect parts were identified and isolated. The methodologies and process chosen to identify counterfeit parts will be reviewed and an assessment of the results will be presented along with the defects found in relation to the defect types reported in relevant test standards.

As DMSMS and Obsolescence relate to printed circuit boards (PCB),there is an ever increasing need for maintaining spare and replacement boards for legacy systems that are operating well past their intended lifecycle. This is especially true in the transportation,medical,automotive,aerospace and military industries. Many times,the original manufacturer is no longer in business or no longer has the fabrication data. In these cases,there is the urgent need to precisely regenerate this manufacturing data from existing remaining parts,film,paper drawings,etc. Exact “Form,Fit and Function” is required so newly fabricated PCBs will “handshake” or integrate properly with existing systems and to avoid costly environmental or functional testing. Replacement parts that are not identical in all ways to the original parts must be treated as a new design,which is a very expensive and time consuming proposition. There are many techniques that have been used to re-engineer PCB’s. Each has distinct advantages and disadvantages. Some of the techniques covered in this paper are:
-Manual hand probing for Bill of Materials (BOM) and Netlist generation,
-Optical and X-ray imaging systems for capturing connectivity and PCB geometry information.
-Flying Probe Test (FPT)and Bed of nails test systems for obtaining and validating connectivity information
-Techniques that create data in usable formats,and even permit information to be imported into Computer Aided Design (CAD) systems,etc.
Optical and X-ray images of internal PCB layers will be presented along with discussion about the pros and cons of each image acquisition process. Destructive and non-destructive techniques used for obtaining inner layer PCB information will be discussed. The required manufacturing data formats such as Gerber/Drill data,IPC-2581,etc. can be generated using some of the PCB Re-engineering techniques that are presented in this paper. Other data formats required for board testing and repair,such as Netlist (IPC-D-356A) and Schematics,will be covered in detail. In some cases,replacement components may no longer be available and some redesign may be needed which requires moving the data back into a CAD system. In addition,some organizations use these processes to “miniaturize” existing PCBs while maintaining existing functionality. This paper provides a basic understanding of the various techniques for PCB Reengineering that are available today in support of addressing DMSMS and Obsolescence as they related to TLCM.

In recent years,a growing number of electronic devices are being incorporated into automotive and other high reliability end products where the challenge is to make these devices more reliable. The package size of the devices is largely driven by the consumer industry with their sizes getting smaller making it harder to assemble and be reliable at the same time. For automotive and other high reliability electronics product,it is of the utmost priority to secure high reliability because it directly involves human life and safety. Challenges include selecting an appropriate solder alloy and having good reliability of the solder paste flux. For solder alloys,much development has been done and is in progress. For the solder paste flux,it is important that the flux intended for automotive and other high reliability applications should have reliable insulation resistance even in an atmosphere of high temperature and high humidity. To meet these requirements,a type of ‘crack free' flux paste was developed to inhibit cracking under extreme environments making it more reliable with stringent surface insulation resistance and electro-migration criterion from automotive and other high reliability product manufacturers. Crack-free flux residues help to prevent electro-chemical migration caused by moisture entering through the flux residue cracking. In addition,crack-free residues act as a type of conformal coating providing a consideration to assemble without conformal coating use for certain applications. Experiments were carried out to test the reliability of the flux according to various industry electro-chemical migration and dew test standards using IPC and JIS (Japan Industrial Standard) test boards. The flux residue showed no indication of cracking after pre-conditioning from-30°C to 80°C accelerated thermal cycling for 1,000 cycles followed by testing with no evidence of electro-chemical migration with a variety of board line widths and spacings used on the test boards. Printing,wetting,voiding and reflow tests with components were also carried out to make sure that the developed solder paste was appropriate for high volume manufacturing with results reported.

It is well known that structures at fine pitches with flux residues are more susceptible to corrosion issues and electrochemical migration (ECM) problems. Characterization of flux residues in terms of ECM are commonly characterized using SIR testing. A key parameter of the SIR test is the comb pattern used and gap between the electrodes. The current B24 and B25 with their 500 and 318µm gap patterns are not representative of fine pitch. It has been proposed to use a 200µm gap pattern,and this paper describes an intercomparison that validates the introduction of the 200µm gap pattern. A new test board was used that included the B24 and B25 patterns with an additional 200µm pattern,with each pattern duplicated,giving six in all. This work was motivated by an update to the current IEC 61189-5-501[1]. A protocol for the testing was developed that took a standard test rosin flux and defined the flux loading and thermal conditioning. Seven laboratories took part from five countries. The test boards were prepared centrally and then tested in the seven laboratories,and the results analyzed to validate the usage of the 200µm pattern. The paper describes the intercomparison and the data analysis.

No-clean solder pastes are widely used in a number of applications that are exposed to wide variations in temperature during the life of the assembled electronics device. Some have observed that cracks can and do form in flux residue and have postulated that this is the result of or exacerbated by temperature cycling. Furthermore,the potential exists for the flux residue to soften or liquefy at elevated temperatures,and even flow if orientated parallel to gravity. In situations,such as in automotive electronics,where significant temperature cycling is a reality and high reliability is a must,concern sometimes exists that the cracking and possible softening or liquefying of the residue may have a deleterious effect on the electrical reliability of the flux residue. This paper will attempt to address this concern. For this work,two commercially availableSAC305Type 4no-clean solder pastes,one halogen-free (ROL0) and the other halogen-containing (ROL1),will be examined. In accordance with IPC J-STD-004B,these solder pastes will be printed and reflowed,using the same common air reflow profile,on to IPC-B-24 SIR test boards. After reflow,each solder paste will have boards set aside for constant room temperature exposure,-40°C to +125°C temperature cycling and -55°C to +175°C temperature cycling. For the two temperature cycling scenarios,boards will be orientated both perpendicular and parallel to gravity in the temperature cycling chamber. Upon completion of the temperature cycling,the boards will be submitted to Surface Insulation Resistance (SIR) testing per IPC-TM-650 2.6.3.7. The SIR readings will be plotted for each scenario and compared.

Smartphones and tablets require very high flexible and sever bending performance to the Flexible Printed Circuits (FPCs) to fit into their thinner and smaller body designs. In these FPCs the extraordinary highly flexible treated rolled annealed (RA) copper foils are recently used instead of regular RA foil and electro deposited (ED) foils. It is very important to measure the Young’s moduli of these foils predicting the mechanical properties of FPCs such as capabilities of fatigue endurance,folding and so on. Even though the manufacturers use IPC TM-650 2.4.18.3 test method for measuring Young’s modulus of copper foils over many years,where Young’s modulus is calculated from stress-strain curve,it is quite difficult to obtain the accurate Young’s modulus of metal foils by this test method. The S-S curves of copper foils always exhibit a large degree of scattering. In order to cope with the issue,‘Resonance method’ using the resonance frequency of a specimen is proposed to measure the much accurate Young’s modulus. The comparison is made between IPC TM-650 2.4.18.3 and the resonance method in view of calculation of Young’s modulus,accuracy. It is found that Young’s modulus values measured by the resonance method were close to theoretical values than those measured by the conventional method. In addition,the experimental data of fatigue life are utilized to support the accuracy of Young’s modulus values measured by the resonance method.

As a result of the continuous industrial trend towards high density packaging there is a growing demand for highly thermally-stable laminate materials. Although the epoxy resin defines the thermal stability,often the flame retardant used becomes the limiting factor in achieving a higher stability. Recognizing this industrial need,the company has developed a new flame-retardant curing agent,Material A. This is a phosphorus-based polymer which cures epoxy via a very specific mechanism. Common Novolac epoxy resins cured with Material A and a phenol-formaldehyde resin show a Tg>180°C and Td >400°C. In addition to a high thermal stability,Material A also shows a dielectric loss factor lower than commercial phosphorus-based flame retardants.

With complexities of PCB design scaling and manufacturing processes adopting to environmentally friendly practices raise challenges in ensuring structural quality of PCBs. This makes it essential to have a good ‘Design for Test’ (DFT) to ensure a robust structural test. A good structural test implementation starts right at the design of an ASIC wherein,the system application and,the ASIC design itself should be kept in mind for implementing the features to enable testability. Answers to the below four questions are the essence of the first part of this paper.
•What are the aspects to be considered for enhancing ‘DFT’?
•How effectively can the ‘DFT’ be reviewed?
•Is there an intelligent and automated way of doing this?
•At which phase of Product Life Cycle should the DFT review be done,to obtain best value for structural test?
During the course of the DFT review,can we realize a good test strategy for the PCBA? How can the test strategy of the PCBA be partitioned as to what portions of the design can be covered structurally and what is covered functionally,in a way that provides best diagnostics to discover faults? Answers to the above two questions will be addressed in the second part of this paper.

This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scantest system on how we can extend beyond typical manufacturing test:
1.Boundary-scanas a complete manufacturing test system –A boundary-scantest system should be able to cover all the needs of a manufacturing test to be an effective solution.
2.Boundary-scanimplementation during PCBA design stage –This topic will discuss the importance of design for test (DFT) at the early stage of PCBA design to maximize the use of boundary-scan to lower the cost of test while increasing the test coverage.
3.Implementation of boundary-scan beyond typical structural testing –While capturing structural defects are important during manufacturing test,the need for boundary-scan to include other areas beyond PCBA structural testing is now necessary.

Manufacturers test to ensure that the product is built correctly. Shorts,opens,wrong or incorrectly inserted components,even catastrophically faulty components need to be flagged,found and repaired. When all such faults are removed,however,functional faults may still exist at normal operating speed,or even at lower speeds. Functional board test (FBT) is still required,a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price,FBT test costs have not been arrested. In fact,FBT is a huge undertaking that can take several weeks or months of test engineering development,unacceptably stretching time to market. The alternative,of selling products that have not undergone comprehensive FBT is equally,if not more,intolerable. Design for Testability (DFT) techniques are effective ways to reduce FBT test programming complexity. This is accomplished by improving Observability and Controllability attributes. This often implies adding test points,but access improvements can be gained from many design activities. These include JTAG/IEEE-1149.1 boundary scan access wherever they happen to be present. We examine some failure modes and show that many of them need to be tested with FBT. Still others require DFT to enable FBT to detect them. We suggest a more pro-active approach that purposely places boundary scan access to internal circuit locations necessary or instrumental for better tests. This approach requires test and design collaboration during the design process. Designers must understand the test requirements early enough to add the necessary access points so that path sensitization and diagnostic attributes are also improved. When complex measurements are needed to ensure functionality,increased cost of both test equipment price and lack of availability may be limiting factors. Designs can usually accommodate existing ATEs and test set ups,provided this is done during the design process. We propose a parallel design and test engineering activity. We argue that while the potential benefits are great,the added costs are insignificantly small.