Due to the ongoing trend towards miniaturization of power components,the need for increased thermal conductivity of solder joints in SMT processes gains more and more importance. Therefore,the role of void free solder joints in power electronics becomes more central. Voids developed during soldering reduce the actual thermal transfer and can cause thermal damage of the power components up to their failure. For this reason,the company has developed a new technique to minimize the formation of these voids during the soldering process. The result of this development is a universal technique to reduce voids in the liquid solder between component and PCB by applying a mechanic sinusoidal actuation. Primarily the PCB is stimulated by a longitudinal wave with an amplitude of less than 10 µm on the PCB level. During this sinusoidal actuation of the PCB in a defined frequency range,the self-resonances of this area are stimulated regardless of the PCB layout. The low starting frequency of the sweep stimulation ensures a gentle,homogeneous propagation of the vibrations in the PCB without damaging the molecule chains (e.g. in FR-4). The intensification of the frequency causes a stiffening of the PCB substrate,an increase in the elastic modulus,and,because of the reduced damping factor,an improved energy transmission of the liquid solder. Thereby areas with low density,so-called voids are moved out of the solder joint by the vibration. Since a sinusoidal actuation of the PCB in a defined frequency range is actuated over the complete spectrum of this range,all the self-resonances of the PCB in this frequency range are stimulated,too. By this,the liquid solder is stimulated repeatedly by the vibration propagation in a relative shearing motion leading to a reduction of voids in the solder joint. The sweep stimulation onto the components is absorbed mostly by the liquid solder,which protects the components from damage caused by vibration transfer. Positive side effects of the sweep stimulation are the centering of the components on the pad and an optimized spreading of the solder on the pad. The process of void minimization takes place within seconds without causing any significant increase in cycle time.

PCB manufacturers use a wide variety of solder pastes and fluxes including No-Clean,RMA and OA,both leaded and lead-free within their processes. As part of the manufacturing process,components are soldered using reflow ovens and/or wave solder systems. Burnt-in flux residues may result on the PCB surface as well as in and around components. It has been well documented that flux residues can lead to failure mechanisms such as leakage current,electrochemical migration and dendritic growth and these can negatively impact the reliability of the PCB. If OA paste and flux is used,cleaning is required using either a DI-water or chemically assisted aqueous cleaning process. Depending on the degree of reliability required,RMA and No-Clean residues may need to be cleaned as well. Once a manufacturer decides to implement a cleaning process,how does one assess its effectiveness? Based on IPC TM-650 guidelines,there are numerous tests that can be implemented to assess PCB cleanliness. These include ionic contamination,ion chromatography and SIR to name a few. The procedures are well documented and the results can be interpreted through industry developed standards. Ionic Conductivity analysis measures conductivity related to amounts of ionic materials (extracted from the PCB) present in solution and is usually expressed as equivalents of sodium chloride in micrograms per unit surface area (µg NaCl Eq./cm2) of the sample. Ion Chromatography analysis measures individual ionic species (type and level of residue). However,each test is based on total board extraction. As there may be a high contamination area within the PCB that may not be detected with standard ion chromatography analysis,a manufacturer may elect to analyze a specific component or part of a PCB by using a localized extraction method coupled with Ion Chromatography. This study was conducted to assess PCB Cleanliness Assessment Methodologies including visual inspection,Ion Chromatography (IC) and SIR analyses resulting from a spray-in-air cleaning process with benchmark parameters. Seven lead-free No-Clean,RMA and OA paste types were considered. The test vehicle used was the IPC-B-52. Additionally,the authors chose several PCB areas for IC analysis via localized extraction and compared all results for overall cleanliness assessment.

With the wide breadth of component types used in complex electronic equipment,implementation of the European Union Restriction of Hazardous Substances 2011/65/EU/ (RoHS) is a challenge. A low volume,very high mix,manufacturer of complex equipment has tens of thousands of purchased part numbers that encompass a wide range of part types including low risk common off-the-shelf parts from robust suppliers to higher risk specialty parts at niche suppliers. One expectation of the directive is that higher risk items and process materials are measured for the restricted substances. The use of a basic handheld x-ray fluorescence instrument provides a relatively fast and inexpensive way to detect restricted substances. However,interpretation of the results must be done with perspective and judgment. The results and learnings from a physical assessment program using X-ray fluorescence (XRF) analysis are discussed. Substance measurement anomalies can occur due to sample heterogeneity and interference with XRF signal generation and detection. False readings of Hg in Au and Cd in Sn are the result of known measurement artifacts,and can be identified with examination of the spectrum. Melted solder samples can give inaccurate concentration of lead due to segregation and segmentation within the sample during cooling. Plastic parts can be at risk of Cd and Pb non-compliance from pigment or plasticizers. Inaccurate measurements can result from extraneous material in the sample window. Techniques are given for measuring contamination at soldering stations,identifying SnPb or SAC solder use when the sample contains extraneous material,and tips for containing and securing samples for analysis.

Over fifteen years has passed since North America and Europe ceased being the center of worldwide PCB fabrication,and were supplanted by a Far East market with low cost labor,more relaxed environmental requirements,and strong government support. In just a few short years,the superior cost advantages of this new dynamic put volume PCB production in the West out of business,aside for the military and specialty technology applications contained in the few shops that continue to exist today. Recently,however,the conditions which created the current equilibrium appear to be shifting again. In this new dynamic,automation,innovative green wastewater technologies,and next generation process equipment innovations have combined to make new factories capable of achieving rapid ROI for PCB fabrication almost anywhere. This paper means to illustrate this new dynamic,and provide case study examples from the new greenfield installation at the company captive facility in New Hampshire.

Additive Manufacturing has recently been brought into the spotlight as an alternative manufacturing method. While there are many different additive manufacturing technologies,the two that will focused on from the paper’s perspective will be Fused Deposition Modeling (FDM) or Fused Filament Fabrication (FFF),and Direct Metal Laser Sintering (DMLS).Fused Filament Fabrication is the extrusion of a material through a heated nozzle onto a build platform. The material is layered until a 3 dimensional part is created. This technology allows for fast cooling times and a variety of materials and colors to be printed as well as flexibility for the creation of 3D objects. DMLS technology is used to print metal parts,where a bed of powered metal is sintered with a laser,then a roller levels another layer of powder over the sintered layer and the laser sinters it again,bonding the melted metal to the layer below it. This is continued until the part is finished. The company is utilizing both of these technologies to help with the manufacturing and product development process for its customers as well as internal use. The company facility utilizes the FFF printers for quick turnaround of prototypes for customer products or processes as well as for internal jig and fixture use on the assembly lines. The DMLS technology is used for customers who desire to see their product prototype in metal for visual or functional purposes as well as internal use for tooling for equipment or projects. As the technologies are used the company is using the current uses as use cases for more areas that additive manufacturing can be implemented along the assembly process,as it is currently used in the earlier stages of development. This paper will review some of the various types of additive manufacturing used and will show how some of the additive manufacturing is being used in a supply chain solution provider environment.

Wetting balance testing has been an industry standard for evaluating the solderability of final finishes on printed circuit boards (PCB) for many years. A Wetting Balance Curve showing Force as a function of Time,along with the individual data outputs “Time to Zero” T(0),“Time to Two-Thirds Maximum Force” T(2/3),and “Maximum Force” F(max) are usually used to evaluate the solderability performance of various final finishes. While a visual interpretation of the full curve is a quick way to compare various test results,this method is subjective and does not lend itself readily to a rigorous statistical evaluation. Therefore,very often,when a statistical evaluation is desired for comparing the solderability between different final finishes or different test conditions,one of the individual parameters is chosen for convenience. However,focusing on a single output usually does not provide a complete picture of the solderability of the final finish being evaluated. In this paper,various models here-in labeled as “point” and “area” models are generated using the three most commonly evaluated individual outputs T(0),T(2/3),and F(max). These models have been studied to quantify how well each describes the full wetting balance curve. The solderability score (S-Score) with ranking from 0 to 10 were given to quantify the wetting balance curve as the result of the model study,which corresponds well with experimental results.

The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon,it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f,during which identical sets of test vehicles were assembled at multiple locations,in accordance with IPC J-STD-001,Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.

Ever since there has been a widespread usage of surface mount parts,the trend of continued shrinkage of devices with ever finer pitches has continued to challenge PCB assemblers for the rework of same. Todays’ pitches are commonly 0.5 to 0.4mm with packages of tiny outline sizes 5 -10mm square,making the rework of such devices a challenge. In addition to the handling and inspection challenges associated with such devices comes the board density. Spacing to neighboring components continues to be compressed so the rework techniques are constantly challenged so as not to damage neighboring components. The objective of any rework process is to duplicate as closely as possible the original manufacturing process but not disturbing neighboring components while at the same time meeting the original specifications and assembly criteria of the PCB. For the rework of a given area or bottom-terminated device this is typically accomplished by using a miniature version of the original printing SMT stencil albeit for the site location only. That being the process that will be characterized in this study,there are two basic types of stencils which can be used to print solder paste onto the PCB. In one case the miniature rework stencil is a shrunken version of the SMT stencil being made from some version of stainless steel of the same thickness of the original stencil. In the other configuration the rework stencil is a single use type made from a flexible plastic film and is adhesive-backed.

Certain types of nano-coated stencils dramatically improve the transfer efficiency of solder paste during paste printing. These nano-coatings also refine the solder paste brick shape giving improved print definition. These two benefits combine to help the solder paste printing process produce an adequate amount of solder paste in the correct position on the circuit board pads. Today,stencil aperture area ratios from 0.66 down to 0.40 are commonly used and make paste printing a challenge. This paper presents data on small area ratio printing for component designs including 01005 Imperial (0402 metric) and smaller 03015 metric and 0201 metric chip components and 0.3 mm and 0.4 mm pitch micro BGAs. The aperture area ratios studied range from 1.06 down to 0.30. The effects of nano-coatings are studied and compared to uncoated laser cut,fine grain steel stencils. Stencil thicknesses are varied from 0.003 inch (75 µm) to 0.004 inch (100 µm) and to 0.005 inch (125 µm). Solder paste powder size is varied including IPC Types 3,4 and 5. The effects of all of these variables are examined in relation to small aperture area ratios. Based on the results of the work a set of guidelines for stencil thickness,stencil nano-coating and solder paste type will be proposed in order to achieve good solder paste printing results.

As a surface finish for PCBs,Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized. Gold ball bonding with 25um diameter wire was performed. Printed circuit boards (PCBs) were surface mounted prior to the wire bonding process with Pb-free solder paste with water soluble organic acid (OA) flux. The standard gold ball bonding process (ball / stitch bonds) was attempted during process development and pre-production stages,but this process was not stable enough for volume production due to variation in bondability within one batch and between PCB batches. This resulted in the standard gold ball bonding process being changed to stand-off-stitch bonding (SSB) or the ball-stitch-on-ball (BSOB) bonding process,in order to achieve gold ball bonding successfully on PCBs with an ENEPIG finish for volume production. Another area of concern was pad metal lifting (PML) experienced on some PCBs,and PCB batches,where the palladium (Pd) layer was completely separated from nickel (Ni) either during wire bonding or during sample destructive wire pull tests,indicating potential failures in the remainder of the batch. Evaluation of failed PCBs was performed using cross-section analysis,X-Ray Fluorescence (XRF),and Scanning Electron Microscopy (SEM)/Energy Dispersive x-ray Spectroscopy (EDS),which identified process issues,such as inclusions,or hyper corrosion which caused either localized or complete separation of the Pd from Ni layer. Through extensive investigation,using 8D and Kepner-Tregoe problem solving methods,solutions to the problem were discovered in the majority of cases,even though the exact root cause remained unclear due to multiple PCB manufacturing variables being changed at the same time.