Due to the arrayed nature of the Computed Tomography (CT) Detector,high density area array interconnect solutions are critical to the functionality of the CT detector module. Specifically,the detector module sensor element,hereby known as the Multi-chip module (MCM),has a 544 position BGA area array pattern that requires precise test stimulation. A novel pogo-pin block array and corresponding motorized test socket has been designed to stimulate the MCM and acquire full functional test data. The pogo-pin block design has specific features which capture and guide the pogo-pins while still allowing for easy pin replacement at the test vendor. In addition,the socket design includes many unique design elements,including built-in protection for the pogo-block from user access,thermal control considerations,and stop features to prevent over clamping. Additional mechanical design features to blind-engage a flexible circuit with the MCM will be discussed. The entire socket and pogo-block system is replicated to create a multi-socket tester that is currently deployed at the OEM vendor. This test system enables full characterization of the MCM including gain connectivity testing and full linearity testing of the device. Various additional aspects of the test system will be discussed,including software control of the socket and data collection of the entire signal chain. This type of test socket architecture can be a model industry example for in-circuit test as well as for final functional testing of a BGA type device.

Automated Optical Inspection (AOI) is advantageous in that it enables defects to be detected early in the manufacturing process,reducing the Cost of Repair as the AOI systems identify the specific components that are failing removing the need for any additional test troubleshooting. Because of this,more Electronic Contract Manufacturing Services (EMS) companies are implementing AOI in to their SMT lines to minimize repair costs and maintain good process and product quality,especially for new component types. This project focuses on the testing of component package 03015 which is challenging for AOI. Highly-automated and effective test methods are becoming a more and more important topic in our industry today. Advances in modern manufacturing technologies have been making factories smarter,safer,and also more environmentally sustainable. Finding and implementing smart machines which provide real time information is critical to success. Currently we have been successful in using 2D/3D AOI for production; however not for the upcoming 03015 components. Therefore,we are working with AOI vendors to ensure successful testing of this component type,with a special emphasis on optimizing algorithm threshold settings to detect defects. We have been working with five AOI vendors with 5 test vehicles (PCBAs). Each PCBA board has 246 components with three different pitch sizes (100µm,150µm,200µm). The results of Attribute GR&R,Defect escapes,and False Call PPM (parts per million) will be presented. Based on the data which we received up to now,every set of data (5 sets – still waiting for results of AOI system 3) is from the algorithms of 2D AOI although some machines have the3D AOI capability. These machines have shown different levels of performance. AOI system 5’s results have an excellent acceptable level for Attribute GR&R; both AOI system 5 and AOI system 6 have only several percentage points of a Defect Escape rate. However,this study is just in its infancy; more improvement and testing will be performed. We will continue to provide new test results from all suppliers.

The industry continues to face the challenges associated with BGA,QFN/BTC,and LED packages. The demand for more performance by consumers drives change,which results in greater component density. Component density on printed circuit boards continues to decrease with a corresponding increase in component complexity and reduction in pitches. Good examples of these industrial trends are smartphones,tablets and wearables. In modern production lines,the complexity of these devices drives manufacturers to rely on automated equipment and strict production processes to control variables such as paste deposition volumes,reflow times,and component placement when working with new boards. However,in a rework scenario,controlling all of the variables required to remove and replace one component is challenging. Each of the variables involved with soldering these devices require management on an individual basis. Herein lies the challenge. Many rework processes are still manual ranging from hot air pencils to automated rework machines. These tools are required to duplicate the production process on an individual level. Solder balls up to one thousand I/O and a pitch of 0.35mm on a BGA are becoming more common than 0.4mm or 0.5mm in a package size of 14mm square. QFNs,traditionally,are difficult to rework due to their excellent thermal characteristics. QFNs with a0.35mm pitch and double row terminals on the perimeter and various size ground pads in the middle are increasingly common. LED technology has seen a massive growth,with larger packages and higher wattage output in today’s leading edge printed circuit boards. Higher wattage output requires the use of metal backplanes to dissipate the heat. Contrast the backplane requirement with a relatively low temperature lens and the challenges become evident. This requires more thermal energy in rework without melting the case of the LED. This is a different situation to when LEDs first became mainstream. This paper will show rework processes for all of these challenging components.

The electronics industry has widely adopted Sn-3.0Ag-0.5Cu solder alloys for lead-free reflow soldering applications and tin-copper based alloys for wave soldering applications. In automated soldering or rework operations,users may work with Sn-Ag-Cu or Sn-Cu based alloys. One of the challenges with these types of lead-free alloys for automated / hand soldering operations,is that the life of the soldering iron tips will shorten drastically using lead-free solders with an increased cost of soldering iron tool maintenance/ tip replacement. Development was done on a new lead-free low silver solder rework alloy (Sn-0.3Ag-0.7Cu-0.04Co) in comparison with a number of alternative lead-free alloys including Sn-0.3Ag-0.7Cu,Sn-0.7Cuand Sn-3.0Ag-0.5Cu and tin-lead Sn40Pb solder in soldering evaluations. Tests included solder alloy spread tests on copper,brass and nickel substrates. Soldering iron tip tests done with low silver cobalt containing alloy showed reduced erosion as compared toSn-3.0Ag-0.5Cu solder alloy. The cobalt in the lead-free solder wire was found to create barrier layers between the iron in the soldering tip and the solder,reducing solder tip erosion by as much as 50%.In addition,Sn-3.0Ag-0.5Cu surface mount soldered component test boards were reworked at the soldered chip component locations with Sn-0.3Ag-0.7Cu-0.04Coand Sn3Ag0.5Cu wire to simulate rework in manufacturing operations. Assessment also included pull tests of the soldered lead-frame component joints. The results of the tests are reported.

Soldering is the bonding of metallic surfaces via an intermetallic compound (IMC). The interaction between thermal energy delivery,flux chemistry,and solder chemistry creates the solder bond or joint. Today,reliability relies on visual inspection,operator experience and skill,control of influencers e.g. tip geometry,tip temperature,and collection and analysis of process data. Each factor involved with the formation of the solder joint is an element of risk and can affect either throughput or repeatability. Mitigating this risk in hand soldering requires the identification of these factors and a means to address them. A new technology,which evaluates the quality of the solder joint by calculating the intermetallic compound formation and provides closed loop feedback to the operator,changes the way solder joints are evaluated in hand soldering. Validation of the solder joint requires the ability to identify the correct solder geometry,detect the transition of solder from solid to liquid,and calculate the intermetallic compound formation without adversely impacting throughput or repeatability. Additionally,to be effective,this validation of the solder connection provides real time feedback to the operator and prompts action based on the response. Implementation of this new technology represents a paradigm shift in the hand soldering industry changing the reliance on visual inspection to control of the formation of the intermetallic compound. The validation technology requires two components,software and hardware. The software component is an algorithm that executes the three-step process to calculate the intermetallic compound. The hardware component incorporates a system to store data at the point of use,process the calculations locally and provide feedback to the operator via a visual go/no-go indicator. The validation technology in concert with visual inspection represents a change to the status quo in hand soldering.

The development of novel interconnection materials for production of electronics is of considerable interest to fulfill increasing demands on interconnect reliability in increasingly demanding environments with respect to temperature extremes,mechanical stresses and/or production limitations. Adhesives are playing an increasingly significant role in the continuously evolving electronics industry. Electrically conductive adhesives have developed to the stage that they offer a viable alternative to traditional solders for applications that demand high reliability in structurally challenging environments. Conductive adhesives are often divided into groups based on conductive directions; Isotropic Conductive Adhesives (ICA) normally provide almost equal electrical properties in all spatial directions,and Anisotropic Conductive Adhesives (ACA) which are insulating in an unstressed state,but provide directional electrical conduction through connections between filler particles and the local connection points. Both ICA and ACA have traditionally demanded a high filler content to ensure adequate electrical connectivity. Epoxy based adhesives are often selected due to the vast selection of combinations availability,and traditionally silver fillers are used for obtaining electrical conductivity in ICA. Silver is advantageous since even its oxide maintains high conductivity. Unfortunately,the high cost of silver prevents many applications from using it. An ICA was developed at a much lower cost where solid silver is replaced with metal coated polymer spheres. The polymer spheres are essentially mono disperse in size and can be specifically chosen for different applications. The silver coating of the spheres is approximately 100 nm thick. Specific applications will be presented that highlight the feasibility of the technology with respect to conductivity,structural reliability and lifetime standards. The deposition of the novel ICA has been performed using a jet printing technology to ensure both precise and accurate positioning,size and volume delivery.

With the rapid trend towards miniaturization in surface mount and MEMs lid-attach technology,it is becoming increasingly challenging to dispense solder paste in ultra-fine dot applications such as those involving chip capacitors or BGA packages,as well as dispensing ultra-fine lines in MEMs lid-attach applications. In order to achieve ultra-fine dots and fine line widths while dispensing solder paste,both the solder material and dispensing equipment need to be optimized. Optimizing the equipment can be very challenging,as there are many input variables that can affect the dispense quality of the solder paste. In this paper we will evaluate the many equipment variables involved in the solder paste dispensing process,and the impact these variables have on the dispense quality of the solder paste.

Surface mount components are commonly evaluated for out-of-plane warpage levels across reflow temperatures. Decision making from these measurements is primarily based on signed warpage of a single component surface,per industry standards. However,signed warpage as a gauge can mislead users when surface shapes are complex,or direction of warpage is uncertain. The presented case study analyzes a range of common surface mount components for signed warpage. This wide ranging case study is used to create newly proposed methods for further defining and characterizing surface warpage in a quantitative manner. Analysis of the case study data focuses on two related surface parameters: signed warpage Signal Strength and surface shape naming. Signal Strength is used to classify samples that are in “transition” between positive and negative warpage directions. New methods are shown to represent these transition areas in signed warpage graphs. Surface shape naming is used to further classify surface types,wherein correlation between shape name and surface mount defects are discussed. Algorithms for calculation of Signal Strength and classifying shape names are offered. Real world examples are used to determine appropriate thresholds for sign transitions and shape names in said algorithms. The study proposes a new,industry wide,approach to how companies present component warpage data.

Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard,readily available device packaging methods in which high-density packaging is achieved by: (1) using standard “packaged” memory devices,(2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads,stacked either 2-high or 4-high,and integrated into a single dual-flat-no-lead (DFN) package. To determine thermal cycle reliability,daisy-chain packages were soldered either using lead-free or tin-lead solder with added additional daisy-chain patterns on the PCB to enable resistance monitoring of the stack at thermal cycling intervals. The 3-D stacks were bonded to the board for improving resistance to mechanical loading such as drop and vibration. A number of 2-high and 4-high 3-D stack assemblies were subjected to thermal cycling in the range of -55°Cto +125°C. The daisy-chain resistances were measured at RT and at 50 cycle intervals during thermal cycling. Test results to 500 thermal cycles are presented as well as images gathered from X-ray and optical microscopy to illustrate damage progression and to establish failure mechanisms. Furthermore,comparison was also made between 2D X-ray and X-ray tomography with optical microscopy to determine effectiveness of these non-destructive evaluation techniques. The paper concludes with a summary and recommendations for the next step of investigation.

The multilayer ceramic capacitor (MLCC) has become a widely used electronics component both for surface mount and embedded PCB applications. The MLCC technologies have gone through a number of material and process changes such as the shift from precious metal electrode (PME) configurations which were predominantly silver/palladium to base metal electrodes (BME) dominated by nickel. Each of these changes were accompanied by both quality and reliability problems. The MLCC industry is now in the midst of an unprecedented set of challenges similar to the Moore’s Law challenges being faced by the semiconductor industry. While capacitor failures have historically been responsible for a significant percentage of product field failures (most estimates are ~30%) we are seeing disturbing developments in the low voltage (<250V) commodity part infant mortality and wearout failure rates.