A study was performed to investigate,evaluate and qualify new reworkable underfill materials to be used primarily with ball grid arrays (BGAs),Leadless SMT devices,QFNs,connectors and passive devices to improve reliability. The supplier of the sole source,currently used underfill,has indicated they may discontinue its manufacture in the near future. The current underfill material is used on numerous circuit card assemblies (CCAs) at several sites and across multiple programs/business areas. In addition,it is used by several of our contract CCA suppliers. The study objectives include evaluation of material properties for down select,dispensability and rework evaluation for further down select,accelerated life testing for final selection and qualification; and process development to implement into production and at our CCA suppliers. The paper will describe the approach used,material property test results and general findings relative to process characteristics and rework ability.

It is well documented that Nano coatings on SMT stencils offer many benefits to those assembling PWBs. With reduced standard deviation and improved transfer efficiency nano coatings can provide,there is also a cost. As PWB assemblers work to justify the return on investment,one key question continues to arise. What is the durability or life of these coatings and what can be done in the print process to maximize the life of the coatings? This paper addresses durability of the coatings in relation to the number of print cycles and underside wipe cycles applied as well as materials used on the underside wipe process. Different parameters will be applied and data will be collected. The results of this study will be summarized to help those using or considering the use of these nano coatings to improve their print process and suggestions will be given to maximize the life of the coatings.

With each new generation,the complexity in the design of flip chip devices,as exemplified by thinner package stack-ups,larger device sizes,and multiple die configurations,is increasing significantly. This is creating new challenges in their surface mount manufacturing and their solder joint reliability. To improve surface mount solder joint reliability under mechanical stresses,such as those imposed under shock,drop,and vibration during transportation and end user handling,the use of polymeric materials to provide added reinforcement to the second level solder interconnects on flip chip ball grid arrays (FCBGA)and package-on-package(POP) solder joints has been proposed as a solution. Some of the common examples of such polymeric reinforcement applications in manufacturing include,but are not limited to,corner glue edge bonding,underfill (UF)application,and epoxy-containing solder pastes. However,as the solder joints’ pitch size and height decreases,control of the extent and uniformity of polymeric encapsulation of second level solder joints becomes more challenging. As a result,solder joint encapsulation materials (SJEM) have been developed to provide a better controlled and localized application process. Unlike other polymeric materials in use today,these SJEMs do not require an additional step for cure,since they are applied before the reflow soldering process step and cure during the reflow soldering process step. Based on past studies on polymer reinforced solder joints,mechanical shock performance generally improved with the application of the polymer reinforcement and was less sensitive to the polymeric material properties as long as the material has acceptable application,curing,adhesion and fracture strength properties. However,thermal cycling reliability is more sensitive to certain material properties of the reinforcing polymer. The glass transition temperature (Tg) and the coefficient of thermal expansion (CTE) are two such properties [1-2]. Materials with a low Tg and a high CTE often lead to accelerated solder joint failure from thermal fatigue. Therefore,the material properties of SJEM and the extent of material coverage on the solder joint both play important roles in optimizing solder joint reliability performance under mechanical and thermal conditions. In this paper,two SJEM material application methods,dispensing and dipping,will be studied for the extent and uniformity of their encapsulation of high density BGA solder joints. The solder joint mechanical shock and thermal cycling reliability from these two SJEM dispensing techniques,which correspond to different encapsulation coverage,will also be analyzed and discussed. From the assembly and reliability test results,both SJEM materials showed process feasibility to be applied,reflowed,and cured with SAC305 solder paste. Both SJEM application methods showed promising mechanical shock and temperature cycle reliability. These material scan be considered as a solution to replace underfills and corner glues for smaller,finer pitch components in the future.

Cleanliness level of PCBs is becoming more and more critical given component miniaturization,component density,and manufacturing practices that include no-clean solder flux. The reliability of high risk circuitry (Class 3-Class 1) assemblies requires clean assemblies with field protection using a conformal coating; including poly-para-xylene vapor deposited films. Residues from the manufacturing process limit the level of adhesion of conformal coating on a PCB. Conventional liquid coatings are limited in their uniformity under,around,and across the component,given the application method. The adhesion on hard to reach areas –one can argue-is not a major concern with liquid coatings,but an argument can be made for leadless components where the power and ground are in close proximity. Poly-para-xylene coating is truly a conformal coating that has the potential to penetrate crevices,bottom side of components,board surfaces,component surfaces and cavities present on the component. The purpose of this paper is to research the value of cleaning under Bottom Terminated Components before Conformal Coating. A QFN surface insulation resistance test vehicle,with sensors placed under the component termination will be used for this research. The designed experiment will study both cleaning and non-cleaning before poly-para-xylene coating. The response variables will be measured: 1.) Visual Inspection of Post Soldering Residues,2.) Site Specific Ion Chromatography and 3.) Surface Insulation Resistance using the IPC TM650 2.6.3.7 test method.

PCB design has evolved greatly in recent years becoming ever more complex. Board density is increasing,component standoff heights are decreasing and long term reliability requirements are greater than ever,particularly for Class III products. Given the quality and reliability demands for complex PCBs,manufacturing processes are qualified; that is,the PCB design,including component and solder paste/flux selection,material compatibility and process steps,must meet the long term reliability requirements demanded and quality standards desired. As a result,cleaning is becoming a mandatory step within the manufacturing process. Analytical tests are key elements to any qualification process. Through the IPC,numerous tests have been developed and have been added to industry standards. In particular,IPC-TM-650,method 2.6.3.7 or SIR (Surface Insulation Resistance) is frequently used regardless of the solder paste/flux type. Per the specification,this test can quantify the deleterious effects of fabrication,process or handling residues on SIR in the presence of moisture. Measuring changes in surface resistance is a standard way of testing cleanliness and long-term reliability of a test board or complete process assembly based on industry standards. There are numerous test vehicle options available to the industry for conducting SIR analysis. This study was designed to compare different SIR test vehicles,from a cleaning perspective,in order to determine which,test vehicle is tougher to clean and therefore challenge the cleaning process. The three (3) test vehicles selected were the IPC-B-52,IPC-B-36 and the SMTA Saber. Each test vehicle was populated with specific components. The authors chose to reflow the test vehicles with water soluble solder paste only,since the high activity flux in the water soluble paste would increase the chance of SIR failure if left partially cleaned. Multiple test vehicles were prepared. Cleanliness verification and validation was completed by visual inspection underneath all components as well as by performing SIR tests. All test vehicles were cleaned prior to reflow and ion chromatography was conducted on selected test vehicles initially to ensure they were free of any ionics. An inline cleaning process was used for all cleaning trials.

PCB board manufacturers engage in a number of wet processes. Water is used ubiquitously in many of these processes for rinsing as well as bath make-up. The impacts of water quality on production processes and product quality are many times ignored. Cleaning surfaces to achieve defined levels of cleanliness in terms of particle and other contamination is now a topic of new ISO standards. Many PCB sites do not use high quality water due to the assumption of high costs. This paper discusses how high purity DI water can be produced at lower costs using a DI recycling approach using a technology called EDI (electrodeionization –which is an electro-membrane technology),in PCB production. A discussion of this new technology that allows lower costs of DI production and recycling will be presented. This paper will also present customer and various third party data on how high purity water reduces contamination build up on parts,during processing,improving product quality and reducing rejects.

The High Density Packaging (HDP) User Group has completed a project evaluating the high frequency loss impacts of a variety of imaged core surface treatments (bond enhancement treatments,including chemical bonding and newer low etch alternative oxides) applied just prior to press lamination. Initial high frequency Dk/Df electrical test results did not show a strong correlation with any of the methods utilized within this project to measured surface roughness. The more significant factor affecting the measured loss is the choice of pre-lamination surface treatment. Most of the new chemical treatment systems outperform the older existing systems which depend upon surface roughness techniques to promote adhesion.

Development of information and the telecommunications network has been outstanding in recent years,and it is required for the related equipment such as communication base stations,servers and routers,to process huge amounts of data in short periods of time. As an electrical signal becomes faster and faster,how to prevent signal delay by transmission loss is a big issue for Printed Circuit Boards (PCB) loaded on such equipment. There are two main factors as the cause of transmission loss; dielectric loss and conductor loss. To decrease the dielectric loss,materials having low dielectric constant and low loss tangent have been developed. On the other hand,reducing the surface roughness of the copper foil itself to be used or minimizing the surface roughness by modifying the surface treatment process of the conductor patterns before lamination is considered to be effective in order to decrease the conductor loss. However,there is a possibility that reduction in the surface roughness of the conductor patterns will lead to the decrease in adhesion of conductor patterns to dielectric resin and result in the deterioration of reliability of PCB itself. In this paper,we will show the evaluation results of adhesion performance and electrical properties using certain types of dielectric material for high frequency PCB,several types of copper foil and several surface treatment processes of the conductor patterns. Moreover,we will indicate a technique from the aspect of surface treatment process in order to ensure reliability and,at the same time,to prevent signal delay at the signal frequency over 20 GHz.

The High Density Packaging (HDP) user group working on high frequency test methods,used for speeds above 2.0 GHz,is developing a way of comparing how sensitive each of the various high frequency test methods are in measuring the effect of moisture content on a laminate material’s dielectric constant and loss. In the completed Phase 1 of this work [1],higher moisture content appeared to cause as much as a 20 percent increase in loss with some test methods. The Phase 2 project work was needed to a develop an effective method of determining the moisture content in high frequency test coupons. Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized in this work.

Due to the arrayed nature of the Computed Tomography (CT) Detector,high density area array interconnect solutions are critical to the functionality of the CT detector module. Specifically,the detector module sensor element,hereby known as the Multi-chip module (MCM),has a 544 position BGA area array pattern that requires precise test stimulation. A novel pogo-pin block array and corresponding motorized test socket has been designed to stimulate the MCM and acquire full functional test data. The pogo-pin block design has specific features which capture and guide the pogo-pins while still allowing for easy pin replacement at the test vendor. In addition,the socket design includes many unique design elements,including built-in protection for the pogo-block from user access,thermal control considerations,and stop features to prevent over clamping. Additional mechanical design features to blind-engage a flexible circuit with the MCM will be discussed. The entire socket and pogo-block system is replicated to create a multi-socket tester that is currently deployed at the OEM vendor. This test system enables full characterization of the MCM including gain connectivity testing and full linearity testing of the device. Various additional aspects of the test system will be discussed,including software control of the socket and data collection of the entire signal chain. This type of test socket architecture can be a model industry example for in-circuit test as well as for final functional testing of a BGA type device.