Pockets of gas,or voids,trapped in the solder interface between discrete power management devices and circuit assemblies are,unfortunately,excellent insulators,or barriers to thermal conductivity. This resistance to heat flow reduces the electrical efficiency of these devices,reducing battery life and expected functional life time of electronic assemblies. There is also a corresponding increase in current density (as the area for current conduction is reduced) that generates additional heat,further leading to performance degradation. This paper will describe the results of a series of experiments performed in an in-line convection reflow oven,using a typical lead free reflow profile,with three types of bottom terminated components commonly used in power management applications. A solder paste flux and alloy with a known high level of voiding was used as the control. This solder alloy is of unique interest,despite its voiding in ambient reflow conditions,as it has shown superior resistance to failure under automotive thermal cycling conditions (-40C to +125C) and vibration. The experimental design was comprised of two levels of vacuum (5 and 20 torr) applied at two levels of time (30 seconds and 60 seconds) while the test assemblies were at or above the liquidus temperature of the lead free solder alloy. Each 2 x 2 factorial was performed on identical printed circuit boards with four (4) different substrate surface finishes,including Immersion silver,Immersion tin,ENIG (Electroless nickel,Immersion gold) and an Organic Solder Preservative (OSP) finish used. Each condition was repeated three times and three controls with no vacuum were also processed for each surface finish. Therefore,a total of 60 component/substrate samples were processed and subsequently examined for voiding using X-ray analysis. The results of this study indicate that the vacuum pressure,time under vacuum and the surface finish have little effect on the results when vacuum reflow is utilized. The use of a low pressure vacuum when the solder alloy is in liquidus conclusively results in a significant reduction of observable voids in each combination of surface finish and reflow process condition.

It is well known that during service the layer of Cu6Sn5 intermetallic at the interface between the solder and a Cu substrate grows but the usual concern has been that if this layer gets too thick it will be the brittleness of this intermetallic that will compromise the reliability of the joint,particularly in impact loading. There is another level of concern when the Cu-rich Cu3Sn phase starts to develop at the Cu6Sn5/Cu interface and an imbalance in the diffusion of atomic species,Sn and Cu,across that interface results in the formation at the Cu3Sn/Cu interface of Kirkendall voids,which can also compromise reliability in impact loading. However,when,as is the case in some microelectronics,the copper substrate is thin in relation to the volume of solder in the joint an overriding concern is that all of the Cu will be consumed by reaction with Sn to form these intermetallics. This paper reports an investigation into the kinetics of the growth of the interfacial intermetallic,and the consequent reduction in the thickness of the Cu substrate in solder joints made with three alloys,Sn-3.0Ag-0.5Cu,Sn-0.7Cu-0.05Ni and Sn-1.5Bi-0.7Cu-0.05Ni. A simple model developed for the reduction of the Cu thickness as a result of the diffusion controlled reaction with Sn to form Cu6Sn5 was found to fit the experimental data well. The results reported in this paper provide an example of the way in which microstructural features that can affect joint reliability are affected by small alloying additions.

Voiding is a key concern for components with thermal planes because interruptions in Z-axis continuity of the solder joint will hinder thermal transfer. When assembling components with solder paste,there is a high propensity for voiding due to the confined nature of the solder paste deposits under the component. Once reflowed,many factors contribute to the amount of voiding in a solder joint such as the reflow profile,designs of the component,board and stencil,and material factors. This study will focus on the solder paste alloy and flux combination as well as profile and board surface finishes. Several alloys have been developed in the last decade to boost performance in high-temperature environments and reliability in thermal cycling tests. These alloys typically consist of SnAgCu with additional elements such as Sb and Bi to modify performance. One of the key barriers to adoption of these alloys has been higher levels of voiding. Previous papers have explored the effect of process and stencil modifications with one or more of these alloys1. The solder pastes include several alloys within the range of compositions suggested for automotive applications in combination with different paste fluxes. The results will compare voiding with various alloys and common board surface finishes.

Solder paste has been used in the surface mount technology for many years. However,a complete understanding of the effect of key powder characteristics on the paste properties is still not achieved. This understanding becomes much more important when new solder pastes with finer powder size are developed for advanced applications. In addition,the effect of other parameters such as time,humidity and temperature may also influence the performance of pastes made with fine and ultra-fine powders. In this work,the influence of key powder characteristics on the reflow property of paste made with powders produced with a proprietary atomizing technology,particularly effective in producing solder powder ranging from 1 to 25 µm,is presented and discussed. Powder characteristics considered are particle size distribution and oxygen content. SAC305 powder were aged at various humidity/temperature conditions. The reflow performance of the pastes made with aged powder was evaluated. Moreover,the oxide layer formed at the powder surface was characterized using Auger Electron Spectroscopy and Transmission Electron Microscopy. The influence of external parameters such as humidity and temperature on the powder is discussed.

High reliability process automation devices require serious protection from harsh environments which can be a combination of moisture,corrosive gases and liquids,salt sprays,large temperature variations,mechanical vibration and fungus. Conformal coatings of various resins provide such range of protection for electronics circuit boards. High levels of residual moisture accumulation in electronics can result in malfunction which can be a serious safety issue. This paper discusses the analytical modelling of moisture diffusion and ingress rate through an Acrylic conformal coating,which is a good choice for addressing corrosive environments use,validated by FEA simulation. Diffusivity of materials is determined experimentally using IPC-TM-650 Method 2.6.28. In comparison,a silicone resin based coating is also considered in the study. Mathematical equations have been developed for the calculation of the characteristic times of moisture diffusion in the Acrylic resin based conformal coating of different shapes and sizes to address topography issues. An argument is presented for use of adequate bake-out schedules for different situations which can be calculated based on the temperature dependency of the moisture diffusion coefficient of polymer materials. The diffusion coefficient of the Acrylic conformal coating was experimentally determined using absorption data by weight gain experiment. Once the diffusivity coefficient is known,a theoretical fickian curve is plotted with the experimental data to confirm agreement of its behavior with the fickian curve. The 99% saturation approach is also used which helps to define the limit of fickian diffusion hence eliminate error caused by non-fickian absorption. In comparison to thick films,thin film layers are thin enough that time to reach equilibrium concentration is relatively short and subsequent transport rates are governed by the diffusion behavior of the saturated film. Several moisture concentration curves were created based on the different compound,size and shape of the coating to understand the variation of moisture concentrations. Finally,based on results and understanding of moisture ingress rate through Acrylic and silicone conformal coating material and considering deployment designed life of the product,proper selection of materials together in conjunction with proper bake-out cycles can be used or created specifically for the products to increase the reliability of the product in the field.

Very low viscosity formulations are often required for very thin conformal coating applications. Solvents are used to reduce viscosity of the formulations and accommodate dispensing needs. Solvent-free coatings are attractive due to their environmental friendliness and ability to allow faster processing for coating lines. Until recently,efforts in developing very low viscosity 100% solids coatings were not successful due to performance requirements such as chemical,heat,and humidity resistance. We have developed a technology that results in 20-30 cP viscosity 100% solids UV curable coatings. We will discuss the performance in reliability tests such as heat and humidity resistance (500 hours at 85 oC / 85 % relative humidity) and corrosion resistance (flowers of sulfur resistance and salt spray resistance). Any change in physical appearance,formation of oxidation spots,and insulation performance were checked after reliability tests. The new coatings can also be cured with long wave length LED light and secondary heat.

A new hybrid ALD/CVD protective coating is being considered as a low-cost alternative to poly-para-xylylene and traditional liquid conformal coatings. All of the typical conformal coatings protect the printed circuit boards. This relatively new process is a hybrid atomic layer deposition (ALD) / chemical vapor deposition (CVD) process that produces a unique and very uniform thin film coating. This film offers improved protective properties compared to the other materials such as poly-para-xylylene and the liquid coatings. Plus,the material may have the added improvement that the costly process of masking components is normally not required. The hybrid coating process is carried out in a small-footprint platform and can process PCBs in a large batch. Results will be shown that demonstrate excellent performance results as tested to standard IPC-TM-650 testing protocols,and an opportunity for a new technology that represents an improvement over traditional conformal coatings and poly-para-xylylene.

Security has become a vital part of electronic products as they handle sensitive data in uncontrolled environments and as they face more and more content protection issues. The paper will introduce the security challenges for smart systems and describe a new security tool box and smart packaging which can be obtained by introducing 3D Nano-materials printed envelope (several meters electrical performance with spacing capability of 50 µm),3D embedded devices into electronic modules (active die in PCB) and multi-die WLP System in Package,with active anti-tamper sensors as well as the combination of all,focusing on both the security performance assessment as well as the manufacturing process.

The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space,but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board –like moving items from a desk to a bookshelf –by embedding components into the board. Leveraging the established buried TLPS (Transient Liquid Phase Sintering)paste microvia technology for z-axis interconnection,“via layers” with TLPS paste inserted into lamination adhesive at the desired interconnect points to the component terminals could be used to connect to embedded components. Ideally,components could be buried at any layer to maximize topside real estate and minimize wiring lengths. The concept of using TLPS-filled via layers to make both connections to buried components and any other z-axis interconnections required on any layer will be explored. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density,core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and laboratory demonstrations of this technique will be presented in this paper.

More and more people and things are using electronic devices to communicate. Subsequently,many electronic products,in particular mobile base stations and core network nodes,need to handle enormous amounts of data per second. One important link in this communication chain is high speed press fit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed press fit connectors have several hundreds of thin,short and weak pins that are prone to damage. Small variations in via hole dimensions or hole plating thickness affect the connections; if the holes are too small,the pins may be bent or permanently deformed and if the holes are too large they will not form gas tight connections. The goal of this project was to understand how rework of these new high speed press fit connectors affects connection strengths,hole wall deformations and plating cracks.