For the last several years, we have seen an increase in liquid metal usage as a thermal interface material (TIM) in the semiconductor industry. The primary reason for this increase is that high-performance computers are using much more power, and consequently, heat dissipation becomes a real issue for those applications. Most of the materials that have been traditionally used in the semiconductor industry, such as thermal pastes or phase change materials, do not perform adequately for these high-power applications. Thus, liquid metals with their high thermal conductivity and low interfacial resistance are increasingly used for these types of applications. Applying liquid metal in a consistent volume by jetting or dispensing can be very challenging. One solution to avoid using the jetting/dispensing process is to use low melting point alloys, solid at the room temperatures, where the melting point is below the operational temperatures of those applications. The problem with most of the industry-known low melting point alloys is that they oxidize quickly and the oxides rapidly degrade the performance of the TIMs. High-Performance Phase Change Metal TIMs would keep all the benefits similar to those of liquid metal TIMs (high thermal conductivity and low interfacial resistance), and because they are in a solid state at room temperature, they can be applied by standard pick and place machines. Because this new generation of phase change materials has a thermal conductivity around 40–50W/m*K, they are less prone to oxidation and their melting point temperature can be as low as 50°C or as high as 120°C.

Thermal interface material (TIM) is an integral part of thermal management strategies for electronic applications. TIM is commonly used in between a heat generating component (e.g. microelectronic packaging) and a heat spreading component (e.g. heatsink or cooling plate) to create an effective path for thermal transfer via phonon transport. Surface imperfections and inherent surface roughness from the heatsink fabrication process can lead to the presence of micro-scale air voids in between the two surfaces. The entrapped air acts as a thermal insulator preventing heat dissipation from the heat generating component and results in conditions that exceed maximum operating temperatures. This increased temperature can reduce the reliability and functionality of the electronic system. Factors impacting the utilization of thermal interface material to fill those air voids is the focus of this research. TIM is a composite of thermally conductive fillers dispersed in a polymer matrix. Higher filler loadings improve the bulk thermal conductivity of TIM in establishing a percolation network. Often the impact of thermal boundary resistance is not considered during the thermal modeling and simulation which can have a significant impact on the overall thermal management of the design. This paper is a continuation of previous work discussing the characterization of thermal performance of TIM as a function of TIM wetting ability and bondline thickness. The current work focuses on the effect of surface conditions on the thermal performance of TIM.

High-density interconnect printed circuit boards (HDI PCBs) technology is evolving to enable further miniaturization and functionality of electronics like smartphones, tablet computers, and wearable devices. Therefore, miniaturization of copper lines and spaces (L/S) down to 5/5μm and possibly even lower is needed to add more layers and components without increasing the size, weight, or volume of the PCB. The development of fully additive fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation miniaturized HDI PCBs. This study reports a fully additive manufacturing method called sequential build-up-covalent bonded metallization (SBU-CBM) for the fabrication of miniaturized copper interconnects. Optical microscopy and scanning electron microscopy (SEM) imaging confirm the formation of robust copper interconnects with a feature size of L/S-5/5μm. Energy-dispersive x-ray spectroscopy (EDX) analysis demonstrates detailed information about selective copper metallization in the SBU-CBM method.

Latent reliability issues with stacked filled microvia designs for complex printed circuit boards fabricated using subtractive-etch processes have been well-documented in recent years. This issue is broadly defined as a weak interface between the plated copper and the blind via target pad. When thermally stressed, the generally weak interface will fracture, especially during forced-convection assembly reflow [1].

While many studies of microvia interfacial fracture focused on conventional electroless copper as the plated through hole (PTH) choice, no recent studies measured the reliability of stacked microvias with a semi-additive process (SAP) using a liquid metal ink technology as the catalytic layer.

To measure the reliability of the liquid metal ink process, a six-layer test vehicle was constructed: Layers 1 and 2 and layers 5 and 6 were fabricated with a liquid metal ink technology for additive processing. The conductive layers of the test vehicle were of 25-micron lines and 50-micron spaces.

Test vehicles were subject to 6× reflow simulation—according to protocols in IPC-TM-650 test method 2.6.27B, Thermal Stress, Reflow Simulation—followed by thermal shock reliability testing of 100 cycles with extremes of -65° to 150° C. IPC D-coupons were populated on the test vehicle with a microvia diameter of 100 microns, for an aspect ratio of 0.33:1. The test vehicle contained two sets of two-stack vias, plated copper filled.

For each thermal stress method, a 5% increase in resistance was considered a failure. However, none of the coupons in this test reached the 5% failure threshold. This paper will cover complete results of this study (and additional data from ongoing testing) to show that this technology holds promise for improvement of stacked microvia reliability.

Critical failures were found on laser-drilled microvias on printed wiring boards (PWBs). The copper-filled vias and their corresponding copper landing pads are on the order of 100 microns in diameter. The goal of this work was to examine the mating surfaces of microvias and pads from both good and failed parts for chemical contaminants that might be preventing metal-to-metal bonding between the microvias and their corresponding pads during electroplating of copper. This, in turn, could lead to detachment and electrical failures. Microvia (MV) samples (MV-1, MV-2, and MV-3) were investigated using Raman and x-ray photoelectron spectroscopy, and both optical and scanning electron microscopies. These analyses revealed cuprous oxide (Cu2O) crystals, 100-500 nm in size, on the interfaces of the vias and pads, especially at or near the rims. The pads and vias on sample MV-2 had the highest amounts of Cu2O contamination. X-ray CT scans showed that vias in MV-2 had cavities in the interior. In contrast, vias in MV-1 were completely filled. From the measurements it was concluded that the cause of detachment between the copper-filled via and its mating copper pad was the deposition of Cu2O crystals at the pad-via interface. A pathway to Cu2O deposition has been proposed whereby insufficient rinsing could leave behind a residual electroless copper (Cu) solution with a high pH along the rims of vias and pads. This high-pH liquid containing copper precursors can potentially lead to the electrolytic deposition of Cu2O at the start of the next step, namely, Cu electroplating.