Increasingly larger surface mount components are being developed in today’s SMT industry. With increasing footprints, maintaining acceptable warpage levels through reflow and/or real-world use is a growing challenge. Undoubtedly, efforts are made to mitigate warpage in both PCB and components. However, there are limits to these mitigation effects and they do not resolve sample to sample variation. Here the question is posed, what if 100% of components and corresponding PCB attach areas are measured for flatness prior to assembly? Could pick-and-place machines selectively pick a “best” matching component from those available, to place on the next PCB that comes down the line?

This paper and corresponding study only lays the foundation to answer these posed questions. It is hypothesized that matching shapes at room temperature based on minimizing gap between attaching surfaces is not the optimal way to make PCB to component matching decisions. Instead, it is suggested that predicting what these shapes will be at critical points in the reflow/reliability profile is the more critical shape matching to consider. In this study, a sampling of matching footprints of PCBs and components are measured under reflow temperatures via common full-field optical metrology techniques. Critical assembly temperatures are analyzed looking to optimize which component should go with which PCB by analyzing all possible combinations through software automation. Hypothetically, this data can then correlate back to room temperature shape combinations for the best overall surface mount reliability.

Raytheon Missiles and Defense, formed a L-Lead (Pb) to LF-Lead-free focus group to understand the metallurgical and manufacturing challenges to transition to a “pure” Pb-free metallurgical system for SMT surface mount technology CCA-circuit card assembly. To better prepare for this transition, a number of studies were initiated to evaluate baseline and next generation lead-free solder pastes. One such study used a temperature programmable heated or “hot-stage” installed on a current X-ray machine for real-time radiographic analysis under a simulated SMT reflow thermal profile. Representative PCB / CCA samples were solder printed with baseline and candidate LF solder paste alloys with and without BTC- bottom terminated components (QFN or MLF 100) devices, then transferred to the X-ray hot stage, which was programmed to run under the appropriate SMT Reflow thermal profile. During the hot stage reflow process, the devices and solder pastes were X-ray-video recorded with void density measurements made after reflow. Real-time radiographic imaging of hidden solder pastes under MLF 100s revealed solder joint and voiding formation mechanisms that differed from each of the various solder pastes evaluated. Radiographic results also demonstrated that solder paste wetting behavior correlated to both air + process void formation mechanisms. Moreover, a strong statistical correlation was observed between low void density versus high shock performance of the same baseline and LF solder paste alloy candidates evaluated in another parallel mechanical testing study.

Mainstream manufacturing testing strategies involve structural tests including optical inspection, structural defect finding, such as opens, shorts, missing and catastrophically defective components. This strategy, however, still leaves a great deal of potential faults, especially if the unit under test (UUT) is operating at high speed. Typically, high-speed testing, if performed at all, is left for a later stage of assembly. For example, while the structural tests can be performed on a panel containing several circuit boards, functional testing at high-speed is done only after the boards are separated, powered up and low-speed functional tests have passed. Moving high-speed testing up to an earlier test stage can save the costs of functional tests later. In many cases, if the high-speed controller is found to be faulty, it can be replaced during the structural test stage. This paper investigates ways that manufacturing defect analyzers (MDAs), in-circuit testers (ICTs), functional board testers (FBTs), and system level test (ST) automatic test equipment (ATE) can be augmented by a high-speed bus tester (HSIO) to provide at-speed tests in parallel with structural test. The article will discuss how this capability can be integrated into existing manufacturing test stages and examine the economic benefits of such an approach. It will also demonstrate the economic benefits of bringing high-speed test into the board test rather than perform those tests as part of the system level testing.

In recent years, Neural-Network based deep learning models has demonstrated high accuracy in object detection and classification in digital image processing. Manufacturing industry has successfully implemented prototypes and small-scale deployments to employ AI models for quality inspection. Proven that AI-assisted quality inspection can improve inspection accuracy, operation throughput and efficiency significantly through those prototypes and small-scale deployments. In past two years, two papers “A Framework for Large-Scale AI-Assisted Quality Inspection Implementation in Manufacturing Using Edge Computing” and “A Study of AI Models Benchmarking for Quality Inspection Implementation in Manufacturing Using Edge Computing” were presented at IPC APEX, which discussed the challenges in large-scale deployment of AI models for quality inspection operation, and the IT architectural decisions to fulfill the OT requirement and inference performance requirement at the edge.

This paper continues the discussion on the operational challenges at the edge and deep dives into data archiving and CI/CD (Continuous Integration/Continuous Delivery). It also discusses the technical challenges to meet the security requirement at the edge. A framework for data archiving and Edge CI/CD implementation is presented.

Corrosion is the most dominant failure mode in electronic products. In many cases, the failure seed is corrosion contamination already on the soldering leads before the assembly that propagates over time and is accelerated by humidity, temperature, and acidity in the environment. The corrosion degrades the board to failures later in the production post-assembly testing, and during the product's life cycle.

We present a method for mass real-time early detection of corrosion contamination on electronic components during the mounting pick-and-place process. The method is based on the correlation between the light reflectance from the soldering leads during their placement photography and the extent of the corrosion. Corroded leads have significantly rougher surface and pitting spots than pristine leads. As a result, they reflect light differently. The difference in their appearance can be detected by AI forensic analysis of the component’s pictures. An AI model correlating the leads finish with their corrosion content and progression level is presented, and its performance on mass scale data is analyzed.

We further present a real-life study on how corroded components were detected during the pick-and-place process only to fail during the ICT testing. The post-failure SEM/EDS and cross-section analysis confirm the AI failure predictions on multiple components with corrosion during full-scale production.

The presented method is deployed on multiple production lines inspecting all components without affecting throughput while flagging contaminated components that are unsafe. The accuracy of prediction is over 99.5% tested on over 2.5 billion components.

For the last several years, we have seen an increase in liquid metal usage as a thermal interface material (TIM) in the semiconductor industry. The primary reason for this increase is that high-performance computers are using much more power, and consequently, heat dissipation becomes a real issue for those applications. Most of the materials that have been traditionally used in the semiconductor industry, such as thermal pastes or phase change materials, do not perform adequately for these high-power applications. Thus, liquid metals with their high thermal conductivity and low interfacial resistance are increasingly used for these types of applications. Applying liquid metal in a consistent volume by jetting or dispensing can be very challenging. One solution to avoid using the jetting/dispensing process is to use low melting point alloys, solid at the room temperatures, where the melting point is below the operational temperatures of those applications. The problem with most of the industry-known low melting point alloys is that they oxidize quickly and the oxides rapidly degrade the performance of the TIMs. High-Performance Phase Change Metal TIMs would keep all the benefits similar to those of liquid metal TIMs (high thermal conductivity and low interfacial resistance), and because they are in a solid state at room temperature, they can be applied by standard pick and place machines. Because this new generation of phase change materials has a thermal conductivity around 40–50W/m*K, they are less prone to oxidation and their melting point temperature can be as low as 50°C or as high as 120°C.

Thermal interface material (TIM) is an integral part of thermal management strategies for electronic applications. TIM is commonly used in between a heat generating component (e.g. microelectronic packaging) and a heat spreading component (e.g. heatsink or cooling plate) to create an effective path for thermal transfer via phonon transport. Surface imperfections and inherent surface roughness from the heatsink fabrication process can lead to the presence of micro-scale air voids in between the two surfaces. The entrapped air acts as a thermal insulator preventing heat dissipation from the heat generating component and results in conditions that exceed maximum operating temperatures. This increased temperature can reduce the reliability and functionality of the electronic system. Factors impacting the utilization of thermal interface material to fill those air voids is the focus of this research. TIM is a composite of thermally conductive fillers dispersed in a polymer matrix. Higher filler loadings improve the bulk thermal conductivity of TIM in establishing a percolation network. Often the impact of thermal boundary resistance is not considered during the thermal modeling and simulation which can have a significant impact on the overall thermal management of the design. This paper is a continuation of previous work discussing the characterization of thermal performance of TIM as a function of TIM wetting ability and bondline thickness. The current work focuses on the effect of surface conditions on the thermal performance of TIM.