IPC J-STD-004B standard prescribes general requirements for the classification and testing of soldering flux for high qualify interconnections. This standard defines the classification of soldering materials through specifications of test methods and inspection criteria. The materials include liquid flux, paste flux, solder paste flux, solder preform flux, and flux-cored solder.

This research will use the proposed IPC-53 Surface Insulation Resistance (SIR) test patterns by means of an open comb (2D) and closed comb (3D to simulate a component over the comb pattern). The 2D open comb has uniformity of conductor spacing, sheet resistance, and flux outgassing. The 3D-closed comb simulates the effect of leadless or bottom-terminated components, which have non-uniform sheet resistance and flux outgassing.

The response variables will include SIR testing and visual imaging. The objective is to investigate IPC test method improvements for characterizing soldering fluxes using leadless components with narrow pad-to-pad spacing.

Crimped electrical contact reliability is controlled through strict manufacturing processes and verifications, including pull force testing. Cable and wire harness assemblies’ standards provide the minimum pull force for reliable cables. However, in practice, failures occur at a much higher tensile strength than the minimum required.

The first section of this paper reviewed 780 pull force tests provided by NASA that were analyzed to determine how the data compare to NASA’s pre-existing requirements from cable/harness standards. The measured tensile strength of most of the contact/conductor pairs exceeded the minimum pull force values of NASA-STD-8739.4 and IPC/WHMA-A-620 by at least 100 %. The contact/conductor pair samples’ tensile strength followed a normal distribution with an average tensile strength that was at least 182 % of the minimum requirement, and all samples analyzed passed pull force testing. In addition, the 95 % confidence interval of the average tensile strength distributions for several contact/conductor pairs was plotted as error bars to show that the contact/conductor pairs will meet and surpass the requirements.

The frequency of pull force testing can be problematic for projects because of the cost and availability of spare contacts for the destructive test. It is possible to reduce the frequency of pull force testing if at the beginning of the production run, the conditions of the crimp tool and materials are verified, and the settings of the tool remain unchanged throughout the process. However, the project needs to evaluate the impact to risk from reducing the frequency of testing prior to implementing process changes.

Today’s electronics industry is grappling with increasing demand for more customized products, shorter development cycles, supply chain disruptions, and tighter margins. In the PCB manufacturing market, SMBs now predominate; lifecycle processes are often siloed and handled by geographically disparate teams. Having already established that Design for Manufacture (DFM) and Supply Chain confirmation are vital and valuable components in the product lifecycle, we propose that the next logical step is bringing collaborative analysis capabilities to the cloud to create a digital twin of the PCB lifecycle and align all stakeholders with a common goal.

This paper reviews market trends for adoption of cloud-based tools, correlated from independent research and publicly available sources. Real-world case studies are used to examine how cloud-based DFM and collaboration is changing the playing field by enabling egalitarian access to information that affects planning, influences decisions and reduces time-to-market.

The soldering of THT components through solder waves is a thermal process. However, current design rules, guidelines and guideline catalogs do not map the soldering heat requirement of a solder joint. Therefore, this approach cannot ensure sufficient solder fill according to IPC-A610 at the design stage. This requires objective models for evaluating the design data concerning manufacturability. These models have considerable potential, both technologically and economically. In addition to automated manufacturability checks, the automatic and model-based determination of optimized soldering programs results in potential reduction of scrap, shorter process development and more robust processes. Extensive studies of experimental, numerical and analytical models for the prediction of minimum solder fill are the basis for successful artificial intelligence (AI)-based modeling of THT-selective wave soldering. On this basis, it is possible to train meaningful AI models and actually validate the solder fill. The mentioned approaches will be highlighted in this paper and it will be shown how they can be profitably applied in practice from electronics design to manufacturing.

An In-containing mid-temperature solder paste (MTS) has been developed and successfully used in mobile phone board-stack soldering with a 200°C peak temperature profile [1]. It is now being tested for a wafer-level package (WLP256) application using reflow profiles with peak temperatures ranging from 200°C (P200) to 240°C (P240). SAC305 was used as the control, which was reflowed using a traditional lead-free soldering profile (P240). With the constant paste-to-ball volume ratio of 1:4, the joint morphology changed with the reflow profiles. Under the 200°C peak reflow, hybrid joints were formed, in which the mixing zone, dominated by the MTS, was present at the PCB side while the area above the mixing zone maintained the original SAC305 morphology. Inside the mixing zone, In was present in the form of a InSn4 (γ) phase, Sn(In) solid solution, and likely, In4Ag9 particles. Increasing the reflow peak temperature to 210°C (P210) and above, the homogeneous joint was formed, which indicated the fully-merged SAC305 ball with the MTS paste during reflow. The homogeneous joint morphology was similar to the traditional morphology of SAC305, in which an Sn dendrite was surrounded by a Ag3Sn precipitate network. In most likely existed in In4Ag9 participles and the Sn(In) solid solution. The temperature cycling test (TCT) was conducted with a -40/125°C and 20-minute dwelling profile. Regardless of the reflow profiles, the MTS outperformed SAC305 in TCT. The P210 profile forming the homogeneous joint, resulted in the best TCT performance, which was more than a 30% improvement than its counterpart using SAC305 paste. The other profiles also improved the characteristic life at least 11% more. Using the same reflow profiles, the MTS had also demonstrated that the drop shock performance (g-force >6000g) was at least comparable to or significantly better than SAC305, in which the P220 (220°C peak temperature) reflow, forming the homogeneous joint with the paste-to-ball volume ratio of 1:2, led to the best drop shock performance—more than 90% enhancement than SAC305. Although the reflow profiles impacted the performance, the failure modes remained similar to SAC305.

There has been increased interest in reducing energy consumption during SMT assembly over the past few years. Increasingly, the environmental, financial, and regulatory effects have been demanding new innovations. Low-temperature solder alloys have also been of increased interest to the SMT industry for a variety of reasons including component sensitivity, step soldering, and reduced energy consumption. However, while the reduced temperature and subsequent energy during reflow have often been listed as a benefit, it has rarely been publicly quantified. In this paper, we quantify the effect of reduced temperature on oven energy usage by recording the actual consumption rate of an oven under different reflow conditions. The demonstrated reduction in oven energy consumption may then be used by manufacturers to evaluate tradeoffs and benefits of low-temperature solders.

In the last few years there have been concerns in the industry especially in the products requiring high reliability when using microvia structures. As a result many fabricators have been mandating push back on complex high layer count designs which has resulted in very conservative rules for designers to use and meet the fabricators capabilities. Some fabricators have also struggled to ensure even simple structures are built reliably and with repeatability. This study was to look at materials which would ensure that more complex structures could be built reliably. Traditional thin fiberglass reinforced dielectric layers can have issues with the lack of resin movement through spread glass necessitating higher resin to glass ratios for the manufacture of stacked microvias. Current industry practice has been to limit designs to staggered vias or to 1-2 layers of stacked microvias. This work extending a previous study presented at Apex 2022 1 will show how a thin hydrocarbon dielectric layer can be used and optimized for stacked microvias that demonstrates solid thermal reliability up to 5 levels of HDI. It also shows there seems to be no indication yet of a ceiling on how many layers could be used and introduces buried vias and how they affect the reliability for offset versus direct attach of via structures.

The space- and other high reliability markets are continuously driven towards an increased use of deeply integrated electronics. The increasing demand for complexity and functionality results in the use of large package components with a high number of I/Os. In order to allow the use of components with high pin counts up to 1752, complex high-density interconnect (HDI) printed circuit board (PCB) technology is required. Reconciling the use of multiple laser-drilled microvia levels in a stacked configuration with the reliability requirements for space is challenging when using heritage dielectric materials. The use of ceramic filled low CTE material allows the manufacturing of complex HDI PCB technology with a high reliability.

The work presented in this paper is part of an ongoing European (Horizon 2020) “COMAP-4S” project on components and macro components packaging for space. The Project is coordinated by SAFRAN ELECTRONICS AND DEFENSE with partners ACB, TUB and NANOXPLORE. The most complex PCB technology targeted within the project is four levels of microvias, requiring the use of low CTE laminate material. The reliability of different microvia configurations from all four levels staggered to all stacked was evaluated using test methods as described in ESA’s ECSS-Q-ST-70-60C standard for qualification and procurement of printed circuit boards. The test results of various material-level reliability tests, interconnection stress testing (IST) and reflow simulation combined with rework and traditional thermal cycling are provided to demonstrate a high reliability of the different via configurations and overall PCB technology.

Every layer interconnect (ELIC) printed wiring boards (PWB) were sourced after D-coupon evaluation per IPC-TM-650 2.6.27B. U.S. and off-shore D-coupons were tested to assess reflow survivability, a prerequisite that demonstrates reliable copper interconnects. Tested chains mirrored configurations designed into the actual 12-layer ELIC PWBs including 11-stacks. The structures, test results, and reflow simulation models are discussed. Evidence of the weak microvia interface was presented to the IPC Technical Activities Executive Committee early 2017. Resistance-temperature measurements recorded during convection reflow assembly identified stacked microvia open-reconnects. Reflow tested daisy chains were cross-sectioned, viewed by optical microscopy, scanning electron microscopes (SEM), and focused ion beams (FIB). Copper fractures were located primarily between the target pad and electrolytic copper-fill. Stacked microvias which fractured during reflow imitated mechanical switches. Opens triggered generally above 215C, remained open, and then reconnected when cooled below 215C. Fractured microvias deceptively appear to function normally, are undetectable at ambient temperatures by in-circuit-tests (ICT), conventional air-to-air (ATA) temperature shock or cycle (TS/TC), and therefore introduce a hidden reliability concern when deployed.

Fractured microvias are simply physical contacts, not metallurgical bonds. Unlike stacked structures, staggered configurations formed using the same process withstood the reflow thermomechanical strain. Layer-to-layer staggered microvia paths provided a reliable high-density interconnect (HDI) alternative to stacked structures as long as there was room to fit the configuration. This provided a temporary window, a brief opportunity, to solve the weak stack dilemma that, unfortunately, was squandered and is now closed. Testing to date suggested U.S. suppliers, in general, are not prepared to supply ELIC constructions with greater than 3-stack microvias, let alone 11-stack microvias, that consistently survive reflow. Stacked microvias with weak copper interfaces are subject to reflow-induced fracture which, therefore, precludes their use in mission-critical, high-hazard environments. Consequently, the U.S. supply base is at a technology disadvantage plagued with issues sourcing ITAR compliant HDI PWBs necessary to address circuit congestion set in motion by increased silicon content and smaller footprints.

This paper presents two key aspects of reliability of ball grid array (BGA) technologies: one aspect for high-reliability and the other for commercial applications. For high reliability, it presents the effect of isothermal aging at the BGA part level to address burn-in requirements for die screening per Mil standard specification. Pull and shear behavior of BGAs with tin-lead and SAC305 solder balls were characterized for a number of components before and after two burn-in conditions (125℃ and 150℃ for 240 hr). The burn-in and fresh BGAs were assembled onto PCBs and then subject to thermal cycling (TC) between –40℃ and 105℃ to determine cycles-to-failures (CTFs) for comparison. Pull and shear strength test results of tin-lead and SAC305 solder balls were presented for CABGA208, CTBGA228, and CVBGA360 with 0.8, 0.5, and 0.4 mm pitches. CTFs in Weibull plots were presented for the SnPb CABGA208 for fresh and burn-in conditions.

The commercial aspect covered low temperature solder ball and solder paste for assembling of BGAs and other components. We evaluated two types of low temperature BiSn alloys with Cu/Ni or Ag additives and with melting temperatures between 139˚C solidus and 174˚C liquidus. The mixed hybrid configuration utilized SAC305 BGAs using SnBiAg alloy solder paste. The low temperature assemblies were subjected to two TCs (–40℃/105℃ and 0℃/105℃). CTF results were presented for CABGA208 with failure analysis performed by X-sectional evaluation.