This paper describes the novel use of Fused Filament Fabrication (FFF) 3D-printing technology to create plastic, positioning and retaining structures directly onto the surface of standard FR4 printed circuit boards (PCBs). The 3D-printed structures are retaining walls that enable the encapsulation and protection of specific, critical or sensitive components and circuits on PCB assemblies. Industries having products operating in harsh environments, e.g., Automotive, use encapsulants and other polymeric materials to provide PCB assemblies with protection from moisture and other external influences. An efficient and cost-effective solution for the protection of critical electronics components is desirable. 3D Printing allows for customization and different PCB assemblies and structures may be manipulated using the same printer. Plastic retaining walls were 3D printed onto modified, IPC-B-24 surface insulation resistance (SIR) Test PCBs as a demonstration of the technology. The materials and equipment used to print the 3D-plastic retaining walls are conventional, relatively low cost, and readily available. The FFF 3D printer, process parameters, and the FR4 PCBs required physical modification and print parameter optimization to achieve robust attachment of the printed retaining walls onto PCB substrates. The retaining walls could be printed in under two minutes, thus enabling the possibility of volume scalability. Design features were incorporated into the printed structures to reduce thermal stress. This case study describes a design, equipment, process, and materials methodological approach for the 3D printing of plastic retaining walls onto PCBs. The retaining walls assist with the encapsulation, protection, and test of critical circuits operating in harsh environments.

Direct Digital Manufacturing (DDM) combines additive and subtractive manufacturing methods to fully fabricate Printed Circuit Structures (PCS). Harnessing the flexibility of additive methods, designers may embed electronics into functional structures. This flexibility is made possible through the additive deposition of structural plastics and conductive pastes in the DDM process. For PCSs, traces are typically formed with a single layer of silver paste deposited through direct ink writing (DIW). Vias are formed by fully filling cylindrical cavities with silver pastes. However, DDM conductive features see performance far below copper and experience via yields far below that of traditional PCBs due to current manufacturing techniques and thermal limitations of the structural plastics.

A method involving stacking conductive traces was developed. This method of stacked 20µm-layers showed a 92% reduction in resistance of a trace when compared to a single-layer trace of equal height. The second method presented in this work involves coating only the walls of the via with conductive material using a novel vacuum extraction technique. Using this method, a 98 percent yield within an array of 50 printed vias has been achieved. Resistances through the via were measured to average 4mΩ. A demonstration PCS is then presented to show the impact these improvements have compared to previous DDM methods. The PCS features comparisons on trace and via resistances, and via yields, in a circuit environment representing typical additive electronics, and shows the potential for additively manufactured electronics to achieve higher levels of complexity and performance.

High reliable lead-free alloys are suitable for high operating temperatures and longer temperature-cycling time. The Innolot alloy,for example, is based on the tin-silver-copper (SAC) metallurgical system and contains additional elements to harden the alloy and to increase its creep strength in order to significantly improve the reliability of solder joints. Compared to traditional SAC alloys, the characteristic lifetime can be enhanced on the base of temperature cycle test (TCT) from -40°C to +125°C or even extended to +150°C.

Assemblies in the automotive industry increasingly require higher reliability for safety-relevant and new emerging applications such as advanced driver-assistance systems (ADAS). Cost-reduction requirements demand a new approach for optimized soldering materials and processes. The investigation in this paper shows that, with an improved alloy composition, the material cost of high reliable alloys can be reduced. Additional cost benefits are achieved by transferring the reflow process to air atmosphere while maintaining high solder-joint quality. This breakthrough was possible due to a combined approach of alloy and flux optimization, which resulted in an innovative, high reliable solder paste system.

This paper will show basic alloy and flux properties as well as TCT results comparing the new formulation with SAC305 and Innolot solder pastes in temperature ranges between -40°C and +125°C, as well as +150°C.

When evaluating solder paste for use, mechanical reliability is one feature of interest. The performance of an electronic assembly in a vehicle, for example, may hinge on a solder alloy’s resilience to vibration fatigue. Test standards exist for vibration fatigue, but those are usually meant to test whole assemblies, not individual solder pastes. The purpose of this study is to evaluate solder pastes for BGA use rapidly and in fine resolution, enabling an informed decision when selecting paste for automotive assemblies. In this experiment, three different alloys were evaluated for their vibration resilience using 1mm pitch PBGA256 packages. The flux system and reflow profiles for the three alloys were kept constant. All tests were conducted at ambient temperature. The test vehicle, fixturing system and test regimens developed for the study will be discussed. Results show meaningful differences between the three alloys. Intergranular fatigue fractures within the solder bulk were observed in tests lasting less than 5 hours. Failure mechanisms for lead-free alloys in isothermal vibration will be discussed, with cross-sectional images from this experiment to demonstrate.

For an automotive transmission control unit (TCU) platform, the bottom ground pad of a high power low-profile quad flat package (LQFP) component soldered to the thermal pad of the PCB had a void specification limit of 25% for optimum heat dissipation. This OEM specification must now be implemented in EMS production with high reliability (Cpk 1.67) and high cost effectiveness. Testing with different solder pastes, stencil designs, stencil thicknesses, and an optimized reflow profile in a standard air convection reflow oven still resulted in 11% PCB assembly scrap with LQFP voiding >25% void limit. When soldering was done in vacuum reflow, LQFP solder voiding met the 25% void specification, but the vacuum reflow oven was rejected because of (a) the significantly higher cost of the vacuum oven; (b) reduced throughput due to increased process time [additional time in the vacuum chamber, longer time above liquidus (TAL)]; (c) more floor space needed to accommodate the longer vacuum oven; and (d) process defects such as solder splash and concerns with increased intermetallics due to a longer TAL.

In this study, printed solder paste was replaced by a single flux-coated solder preform that was picked from a tape & reel pocket with a standard production nozzle and placed on the PCB thermal pad. With the flux-coated solder preform, (a) maximum voiding was 1.67; (c) Product Validation (PV) builds for series production achieved a high Cpk > 1.834; and (d) the standard air convection reflow oven could be used with no additional equipment cost.

The research goal was to establish a limit for the number of rework cycles for Ball Gird Arrays (BGAs) and to determine the clearance required between a BGA and its surrounding components on an assembly without impacting the overall Printed Circuit Board (PCB) and Printed Circuit Assembly (PCA) reliability. This project’s test vehicle is comprised of four different sets of layouts, each utilizing a large plastic of 40×40mm (1.6"×1.6") BGA surrounded by various sizes of BGAs—(3×3mm (0.1"×0.1"), 6×6mm (0.2"×0.2"), 6×8mm (0.2"×0.3"), 8×8mm (0.3"×0.3"), 9×9mm (0.4"×0.4"), 11x11mm (0.4"×0.4"), 17×17mm (0.7"×0.7")—placed at various clearances to the center BGA. The surrounding BGAs consist of various pitches, substrate materials, and package sizes, and are placed at specific clearances—1.3mm (50mil), 2mm (75mil), 2.5mm (100 mil), 3.8mm (150mil), 5mm (200mil), 6.4mm (250mil), 7.6mm (300mil), and 10mm (400mil)—away from the center BGA, which is the rework site. Peak temperatures were recorded using thermo-couples at the surrounding components during each rework cycle. Based on the drop shock reliability test results and cross section of microvias, PCAs were still reliable after two rework cycles as failures were not due to fatigue and via structures were still good and fully intact. Thermocouple results showed that a clearance of at least 10.16mm (400mil) is required for reduced effects of secondary reflow [1]. Examples of secondary reflow effects are the risk of increased void percentage (%), solder joint brittleness, hot tear defects, and PCB delamination. However, this may not be favorable to high-density designs. Nevertheless, secondary reflow is inevitable at all adjacent components due to physical proximity. Alternative soldering methods or physical shielding techniques [2] must be deployed for tight spacings; these will require further study.

Repair of soldered components is a constant necessity in the electronics industry. Product performance enhancement, damaged components, and exchange of wrong placed components are some of the motivations behind a repair. Dispensing and placing a 400 µm pitch component manually is very time consuming and could cause collateral damage to the already populated components. A novel automatic repair method and tools with no human interaction were developed. This method uses the advantages of solder jetting and pick and place in one instrument, making it extremely accurate, reliable, and cost-effective. The use of different alloys including low-temperature soldering (LTS) is feasible. The results show that this technique significantly improves the throughput of the repaired devices.

During the past few years, it has become increasingly difficult to physically rework printed circuit board (PCB) assemblies. Such mundane operations as soldering, desoldering and component replacement have become complicated by extreme micro-miniaturization, the use of lead-free solders, new thermally challenging PCB’s and intricate component packages, such as BGA's, QFN’s and other area array packages, that are difficult to install and remove. As a result, many manufacturers have lost the organic capability to rework modern PCB’s, especially those that incorporate BGA’s, opting to hire outside contractors to perform more difficult repairs. This paper will examine advanced tools and techniques that incorporate infrared (IR) or radiant heating technologies to perform non-destructive, highly reliable and high quality rework on complex area array-laden assemblies. Topics that will be discussed include: advantages and disadvantages of infrared versus convective heating; use of nozzles in BGA/area array rework; optimal IR wavelengths; survey of the most advantageous types of IR emitters; the critical role of bottom-side preheat; simplified thermal profile development; non-destructive thermocouple techniques and the proper use of a non-contact, closed-loop IR pyrometer to maintain the target profile; and advanced rework application tips when using IR technology.

Highly reliable and high-yield prototyping in the early stages of development is crucial for innovations in next generation microelectronic systems to demonstrate the results of research. This prototyping is typically based on the combination of Flip Chip technology, SMD assembly, and sometimes wire bonding; all are used to build a functional system from heterogeneous components.

Prototyping typically consists of low manufacturing volume, with batch sizes ranging from 1 to 50. The stages of prototyping include: pathfinder run, first test, system optimization (including component optimization and layout changes), and manufacture of full batches. To achieve this level of flexibility, tool-less manufacturing is mandatory. For the application of solder paste, solder jetting is ideal for prototyping as no stencil is necessary and paste deposition designs can be quickly modified.

A research project was set up to correlate jetting and soldering quality to monitor changing properties over solder paste lifetime. Solder paste jetting behavior, deposition geometry, tackiness for component placement, and solderability/wettability are properties that define the process quality throughout assembly. The impact of solder paste aging and environmental conditions of jetting and soldering quality was studied using optical profilometry and electrochemical impedance spectroscopy (EIS). An optical profilometer was used to qualify the solder paste after jetting and soldering a defined array of deposits. EIS was used to monitor changes in the solder paste prior to and during its jetting application. This paper will demonstrate how in-depth analysis of solder paste is essential to ensure high-yield processes and high-quality prototyping.

Different types of components with soldered bottom terminations are increasingly used in the electronics industry with the principal objective to improve heat dissipation.

The large areas of the solder terminals are an advantage for the heat to escape. However, if the thermal pad design is not optimal or the assembly process not properly adjusted, big voids could be created in these solder joints. The industry criterion for acceptable voiding for thermal pads wettable area is <50% for class 1, 2 and 3 [1]. But there is no established limit for unacceptable voiding, anything above 50% is treated as a “process indicator” for Class 2 and 3.

As heat dissipation improves with less voiding and single large voids may create hot spots, it is important to achieve as low voiding amount as possible and prevent large voids from forming.

There are many parameters that affect the amount of solder joint voiding. Optimization of the stencil design together with a good choice of solder paste, or solder preforms, and a good assembly process have the potential to significantly lower the thermal pad solder joint voiding and to increase the soldered area.

X-ray images of two typical Quad Flat No-lead (QFN) thermal pad solder joints generated from different solder pastes, but otherwise identical process setup, are shown in Figure 1 (shown in paper).

The actual design of the thermal pads is also important. In this presented study, different thermal pad designs to minimize voiding and maximize soldered surfaces for QFN thermal pad solder joints have been investigated.

The purpose was to find thermal pad designs for standard QFN packages that result in consistent solder joint voiding, well below the acceptable limit [1], and have as large soldered surface area as possible.