High-density interconnect printed circuit boards (HDI PCBs) technology is evolving to enable further miniaturization and functionality of electronics like smartphones, tablet computers, and wearable devices. Therefore, miniaturization of copper lines and spaces (L/S) down to 5/5μm and possibly even lower is needed to add more layers and components without increasing the size, weight, or volume of the PCB. The development of fully additive fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation miniaturized HDI PCBs. This study reports a fully additive manufacturing method called sequential build-up-covalent bonded metallization (SBU-CBM) for the fabrication of miniaturized copper interconnects. Optical microscopy and scanning electron microscopy (SEM) imaging confirm the formation of robust copper interconnects with a feature size of L/S-5/5μm. Energy-dispersive x-ray spectroscopy (EDX) analysis demonstrates detailed information about selective copper metallization in the SBU-CBM method.

Latent reliability issues with stacked filled microvia designs for complex printed circuit boards fabricated using subtractive-etch processes have been well-documented in recent years. This issue is broadly defined as a weak interface between the plated copper and the blind via target pad. When thermally stressed, the generally weak interface will fracture, especially during forced-convection assembly reflow [1].

While many studies of microvia interfacial fracture focused on conventional electroless copper as the plated through hole (PTH) choice, no recent studies measured the reliability of stacked microvias with a semi-additive process (SAP) using a liquid metal ink technology as the catalytic layer.

To measure the reliability of the liquid metal ink process, a six-layer test vehicle was constructed: Layers 1 and 2 and layers 5 and 6 were fabricated with a liquid metal ink technology for additive processing. The conductive layers of the test vehicle were of 25-micron lines and 50-micron spaces.

Test vehicles were subject to 6× reflow simulation—according to protocols in IPC-TM-650 test method 2.6.27B, Thermal Stress, Reflow Simulation—followed by thermal shock reliability testing of 100 cycles with extremes of -65° to 150° C. IPC D-coupons were populated on the test vehicle with a microvia diameter of 100 microns, for an aspect ratio of 0.33:1. The test vehicle contained two sets of two-stack vias, plated copper filled.

For each thermal stress method, a 5% increase in resistance was considered a failure. However, none of the coupons in this test reached the 5% failure threshold. This paper will cover complete results of this study (and additional data from ongoing testing) to show that this technology holds promise for improvement of stacked microvia reliability.

Critical failures were found on laser-drilled microvias on printed wiring boards (PWBs). The copper-filled vias and their corresponding copper landing pads are on the order of 100 microns in diameter. The goal of this work was to examine the mating surfaces of microvias and pads from both good and failed parts for chemical contaminants that might be preventing metal-to-metal bonding between the microvias and their corresponding pads during electroplating of copper. This, in turn, could lead to detachment and electrical failures. Microvia (MV) samples (MV-1, MV-2, and MV-3) were investigated using Raman and x-ray photoelectron spectroscopy, and both optical and scanning electron microscopies. These analyses revealed cuprous oxide (Cu2O) crystals, 100-500 nm in size, on the interfaces of the vias and pads, especially at or near the rims. The pads and vias on sample MV-2 had the highest amounts of Cu2O contamination. X-ray CT scans showed that vias in MV-2 had cavities in the interior. In contrast, vias in MV-1 were completely filled. From the measurements it was concluded that the cause of detachment between the copper-filled via and its mating copper pad was the deposition of Cu2O crystals at the pad-via interface. A pathway to Cu2O deposition has been proposed whereby insufficient rinsing could leave behind a residual electroless copper (Cu) solution with a high pH along the rims of vias and pads. This high-pH liquid containing copper precursors can potentially lead to the electrolytic deposition of Cu2O at the start of the next step, namely, Cu electroplating.

This work compares the influence of a plating additive that has been applied to a commercially available electroless copper system and how its use impacts the morphology of the overall final plated structure. Through testing on insulating materials in addition to single and polycrystalline copper substrates, each electroless Cu solution is shown to be influential in suppressing grain growth in certain crystal orientations, which can lead to significant physical differences across the final plated interface. It is interesting to note that while the degree of epitaxy between the substrate Cu and the electroless Cu can be influenced dependent upon the additive utilized, this can occur independent of the impact between the electroless and electrolytic Cu. To wit, an epitaxial interface between the substrate and electroless Cu is not strictly indicative that an epitaxial structure will occur between the electroless and electrolytic Cu.

The plating additive under investigation is shown to support epitaxial or “bottom-up” recrystallisation for selective grain orientations originating within the substrate material and will typically facilitate grain growth in the (100) and (110) orientations while a solution without the additive supports the (110) and (111) orientations. Such performance is offered as occurring as a result of the characteristic electroless copper surface which consists predominantly of large, but low index {100} facets, in contrast to the smaller but higher order facets {221} that occur when the additive is not employed. When applied to polycrystalline substrates, either of the electroless copper processes considered within this investigation have been shown to facilitate a fully epitaxial structure, which arises from the situation that either of the “preferred” crystal orientations are available within the substrate.

Through careful selection of the additive packages used within an electroless Cu system, there can be significant control gained over how not only the electroless layer itself crystalizes, but also the response of the subsequent electroplated layer as well. Both of these are understood to have significant impact on the physical and mechanical properties of such an interface, which in turn can be influential in achieving the desired overall properties.

Through an increased understanding of how the additives used in a state-of-the-art electroless copper process function, and the impact that they subsequently have on the crystallography of the final deposit, it is anticipated that an improved overall joint integrity can be achieved. It is now considered that a fully epitaxial microstructure across the target pad – ELESS – ELYTC Cu interfaces is desirable as this offers a higher resistance to crack propagation and so enhances overall reliability. This is clearly beneficial in many plating applications, especially those containing microvias, where historically decreasing dimensions and aggressive operational demands in combination with an increased use of stacked BMV designs has led to undesirable interconnect failures around the target pad – electroless Cu – electroplated Cu interface.

The High Density Packaging (HDP) user group has completed a project to evaluate the impact on field reliability of more frequent thermal cycling over more narrow operating temperature ranges such as occur in today’s data center or cloud environments. In the past, printed wiring board field reliability testing assumed just one thermal cycle per day based upon systems begin completely shut off in the evening and circuit temperatures dropping to ambient temperature before being turned on again every morning. Whereas many systems today are rebooted and/or go into a lower power “sleep” mode ten or more times per day. In addition to the above new field application environments, laminate materials today have higher filler content and their mechanical characteristics are different from the less thermally robust phenolic and dicy-based laminate materials used prior to the widespread use of high temperature lead-free solder alloys in board assembly. Note that this project concerns the reliability of the bare printed wiring board and has no connection with any earlier “power cycling” projects which evaluated the reliability of various SMT or PTH solder joint alloys.

The goal of this project was to determine the relative impact on field reliability of more frequent thermal cycling over a more narrow temperature range with less frequent temperature cycling over a larger temperature range using at least two of the laminate materials available today. Interconnect Stress Testing (IST) is one of the recognized standards for measuring the expected reliability of bare printed wiring boards. Although there are other methods, the more practical IST method was selected for determining the impact of these new field conditions on printed wiring board reliability.

For both laminate material test lots, which had several physical differences, the results show that more frequent thermal cycling can significantly affect long term field reliability even with reduced temperature cycling ranges.

Failure of a printed circuit board assembly (PCBA) can occur because of design, manufacturing, mechanical, or electrochemical issues. A propagating fault is a severe failure mechanism in which smoke, electrical arcing, and/or thermal degradation occurs. This paper details root cause failure analysis of a PCBA propagating fault resulting from flexure-induced capacitor cracking. This investigation also included optimization of design and qualification practices to reduce the risk of flexural crack induced failures.

Multilayer ceramic capacitors (MLCCs) are susceptible to flexural crack failure resulting from high strain inducing events, like bending or warpage. The PCBA in this study includes an array of MLCCs that initiated the propagating fault. The MLCCs are in a high strain region of the assembly, which created a short circuit when the flexural cracks propagated across opposing electrodes. The strain level on the MLCCs was exacerbated by adverse warpage conditions and proximity to rigid mounting constraints. Dynamic strains were a contributing factor due to a partially unsupported module directly adjacent to the capacitor array. The dynamic stain on the MLCCs, combined with residual strain, exceeded the strain threshold for the capacitor. Root cause was confirmed through physical analysis and finite element analysis (FEA).

Root cause failure analysis included an assessment to prevent reoccurrence of capacitor induced failures. PCBA and system design factors were evaluated to improve quality and reliability. Future design recommendations were provided, including implementing capacitor spacing guidelines, evaluating layout/component placement to reduce warpage, and employing FEA modeling to evaluate high strain regions.