Next Generation High Density Build-Up PKG Substrate

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In recent years,along with the further progress of network systems,mobile communication systems and high performance
servers printed wiring boards (PWBs),which are key components in these products,are increasing in importance,and are
required for technology innovation.
Especially,the substrates in the field of high-end ASICs require more high density and high performance,and CSP and
Module substrates in the field of mobile application require more high density and downsizing. The demands for the substrate
have been steadily becoming more and more stringent.
This paper introduces a new multi-layer PKG substrate that has been developed to meet these market trends,and has better
features than the conventional build-up substrate. This new multi layer PKG substrate has no core material and is a so-called
coreless structure composed of only high-density build-up layers. This substrate is produced with our original manufacturing
process and has the following features: 1) Light weight (70% reduction),Thin-thickness (less than half),and High density 2)
High reliability 3) Good productivity 4) Green material.

Author(s)
Takashi Shuto,Kenji Takano,Kazuya Arai,Munekazu Shibata,Junichi Kanai,Kaoru Sugimoto
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

Corrosion Factor and Effects of Tin - Zinc Lead-Free Solder on Copper Substrate in Environmental Tests

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We coated copper substrate with tin-zinc lead-free solder (Sn-9Zn and Sn-8Zn-3Bi),and then we performed the following
corrosion tests: the salt mist test,the gas corrosion test,and the weathering test. Following the tests,we visually inspected
specimen surfaces and cross-sections to determine the causes of corrosion and the extent of the corrosion to the base
substrate.
By the surface condition of the Sn-Zn solder following the various tests,it was found that corrosive substances in the
environment (such as sulfur and chlorine) reacted with the Zn in the solder to form corrosive products on the surface of the
solder. After 18 months of the weathering test,cross-sectional analysis revealed that the Sn-Zn solder had been oxidized to a
depth of 10um. However,the copper substrate underneath showed no evidence of corrosion. On the other hand,conventional
Sn-Pb eutectic solder was oxidized to a depth of 20um,and the copper substrate also showed corrosion. We hypothesize that
the corrosion of Zn in the Sn-Zn solder yielded a sacrificial corrosion effect by forming an intermetallic compound layer
(Sn-Zn layer) between the base substrate and the solder. As a result,Sn-Zn solders exhibited corrosion resistance far superior
to that of conventional Sn-Pb eutectic solder.

Author(s)
Hirokazu Tanaka
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

The Use of SAC Solder and Pb-Free Lead Materials in the Repair Scenario

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Much work has been done involving the introduction of RoHS and WEEE Directives across the European Union and the
world. Although the use of Pb is limited in new products and equipment,older Pb-containing materials can continue to be
used for repair of existing systems. As time progresses,these older Pb-containing materials will need to be repaired using Pbfree
components and solders. This paper addresses the concerns of repair centers,which must rework these boards using Pbfree
components and materials.

Author(s)
Mark Woolley,Jae Choi
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

Perspectives on Repaired Lead-Free Solder Joints

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The use of lead-free (LF) solders as a replacement for traditional tin-lead (SnPb) solders in military and high reliability
applications has a number of technical challenges unique to the industry. The need for a metallurgically stable solder joint
under harsh environmental conditions,high stress and shear loading,and long term storage presents a set of requirements that
are significantly different from most commercial applications. It is well documented that processing conditions during
soldering can significantly affect the microstructure and reliability of the joint. Due to the low volume and long life cycle of
military and aerospace electronic assemblies,repair of components is widely employed. While methods for repairing
assemblies using SnPb solders are well established,limited data is available for re -work and repair of LF solder processing,
especially when the resulting joint is a combination of SnPb and LF solders. In this study the influence of repair processing
conditions on the microstructure of LF solders was investigated. Processing parameters such as soldering conditions and
solder composition were used to simulate manufacturing operations. Temperature cycling of components soldered to printed
circuit boards between -55°C and +125°C with SnPb,LF,and mixtures of SnPb and LF solders was performed. Analyses of
the phases present,chemical composition and microstructure of the solder joints before and after temperature cycling were
conducted using optical and electron microscopy to correlate processing conditions to the resulting microstructure. Shear
testing of surface mounted capacitors prior to and after temperature cycling demonstrated a significant drop in shear strength
after temperature cycling. Implications of processing conditions on the reliability and long term stability of the solder joints
will be discussed.

Author(s)
Richard Colfax,Matthew O’Keefe,Patricia Amick,David Kleine,Steve Vetter,Dale Murry
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

'Bridging the Gap’ – Technical Capabilities of a Direct Plate PTH Process

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In contrast to electroless copper,direct metallization processes are inherently less expensive to operate,more environmental
friendly,requires less floor space and are more efficient. Among the three common direct metallization methods,namely
carbon based,conductive polymer based and palladium based,carbon based is the most attractive option,with the lowest cost
and ‘greenest’ ingredients. However,despite past predictions to the contrary,electroless copper processes are still the most
widely accepted through-hole metallization technologies in today’s market.
In their infancies,implementation of direct plate processes at PWB manufacturers produced panels of questionable reliability.
This led many major OEMs to write specifications refusing to accept any alternatives to conventional electroless copper for
through-hole metallization in PWB fabrication. However,despite the lack of official acceptance by certain OEMs,carbonbased
direct metallization is widely used by PWB fabricators where lower costs and environmental concerns are the
industries major drivers.
This paper,focusing on higher technology applications,provides PWB fabricators and OEMs with current up to date
comprehensive data on improvements made to the technical capabilities and reliability of this unique carbon-based direct
metallization system. Additionally,the data supports the acceptance of this direct metallization technology as a viable
alternative to conventional electroless copper processes.

Author(s)
Richard Retallick,Hyunjung Lee,Ying (Judy) Ding,Timothy Spencer
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

Improving Printed Circuit Board Plating with Eductor Agitation

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This paper will review eductor agitation systems at PWB installations to improve the electroplating of printed circuit boards.
Significant environmental and productivity improvements have been realized through the use of carefully engineered clusters
of eductor nozzles. Design parameters,materials of construction,turnover rates and pump selection will be discussed.
Reported benefits such as reduced airborne emissions,faster and more uniform plating rates and prevention of solution
stratification to improve filtration will be reviewed.

Author(s)
Charles Schultz
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

Characterization of Acid Copper Plating Solution for Via-Filling

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The use of acid copper plating process for via-filling effectively forms interlayer connection in build-up PWBs with
high-density interconnections. However,in the case of copper film deposited in a bath,which is greatly dependent on the
effects of additives like via-filling technique,the drop in mechanical properties and the increase in stress in electro-deposits
due to co-deposition of the additives are likely weaknesses. In view of such weaknesses,we concentrated our study on the
mechanical properties of the copper films plated in two types of conformal acid copper plating baths that have been in use for
some time and two types of acid copper plating baths for via-filling.
As a result,selection of suitable additives was confirmed to be of great importance for the acid copper plating bath for
via-filling. The use of the additives that easily deposit with copper was likely to cause drop in mechanical properties of the
film. On the other hand,the fact that the acid copper plating process for via-filling nevertheless deposits a film comparable to
that out of the recognized conformal type acid copper plating bath in the use of the most suitable additives was confirmed.

Author(s)
Hideki Hagiwara,Hideo Homma,Ryoichi Kimizuka
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

What makes the IPC Roadmap Unique?

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Have you ever been confused after you have read two or three different roadmaps and even though they were supposedly
mapping the same attribute in the same time periods,the numbers in the cells were different? Do you often wonder,“Do
these people ever talk to each other”?
Interestingly,even though different all of the roadmaps may be correct. The following list some of the reasons for the
differences and explains the uniqueness of the individual roadmaps.
Industry wide technology roadmapping,which is a fairly new activity in the U.S.,is believed to have been started in Detroit
in the late 80’s when the automotive industry asked their suppliers to present roadmaps of their future products. The focus of
many of these presentations was cost reduction not necessarily technology as the U.S. auto industry was in the middle of
severe cost cutting activities to increase their competitiveness.
There are now numerous national roadmaps. The steel industry,the aluminum industry,and the forging and casting industries
all have published technology roadmaps. In the electronics industry there is also a large number of roadmaps: The National
Electronics Manufacturing Initiative (NEMI) roadmap,The Association Connecting Electronics Industries (IPC) roadmap,
The Semiconductor Industry Association (SIA) roadmap,and the Japanese JISSO roadmap.
Gary S. Vasilash,as Editor - In – Chief of Automotive Manufacturing & Production Magazine once made two broad
statements supporting roadmaps. The first is,roadmaps provide a view to all levels of an organization that goes beyond the
immediate fires that need to be put out and keeping new fires from starting. The second comment was that roadmaps identify
areas where collaboration may be needed in order to achieve leapfrog,not natural incremental,development.
Mr. Ray Kammer,former Director National Institute of Standards and Technology has said “We at NIST love roadmaps…
Roadmaps help us guide our investments and to allocate our resources in accordance with U.S. industry’s priorities. And the
more detailed the roadmaps the better…”
Kammer also said,“The need for two way communication has not subsided. Technology and science are moving too fast.
Global competitive conditions are too fluid. Opportunities are too fleeting,and the technology gaps we must bridge are too
wide to leave communication to chance,or even to individual initiative. Both government and industry stand to gain from a
more systematic and more proactive approach to surveying the technology landscape in electronics.”
“From the government perspective,an example that pops quickly to mind is defense technology. As the Pentagon continues
to transition toward greater reliance on a commercial technology base,there is an even greater need for regular
communication between government and industry. Roadmaps facilitate this communication.”
The Defense department must be alert to trends and developments and to basic research supporting the entire scope of
electronic technologies. It must understand the manufacturing capabilities that underlie these technologies. It also must be
quick to identify research and technology gaps—specialized needs likely to go unaddressed in the commercial sector.
National Technology Roadmaps facilitate this need.

Author(s)
John T. Fisher
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

The European Roadmap

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A unified European roadmap for PWBs does not exist today. It is also most unlikely that a unified roadmap will available in a
foreseeable future time. However,the EIPC has worked together with many European companies and association to define
trends in technology based on the future needs of the industry. This paper will report on some of the trends that are included
in European company roadmaps and the HotCar project. More details have been documented in the European Technology
and Trend Report that has been put together by the German GMM VDE/VDI,the DGO,FED,ZVEI,the EITI as well as the
European Institute of Printed Circuit Boards. Leading companies involved in design of electronic equipment supported this
report. Also PCB fabricators,PCB assemblers as well as materials suppliers for PWBs and companies that develop latest
fabrication methods used to manufacture state-of-the-art electronic equipment. This paper will provide a snap shot on
developments that will impact the European Roadmap for PCBs and will help to guide electronic engineers to select the new
PCB technologies for advanced electronic devices.

Author(s)
Michael Weinhold
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005

Japan’s JISSO Technology Roadmaps

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Japan has a long history of publishing very important technology roadmaps. Some of the Japanese roadmaps published in the
past are:
JPCA Roadmaps
Report on the Technology Roadmap for Advanced Systems Integration and Packaging English version 1998,translated by IPC.What Makes Dreams Come True? A roadmap of microvia technology published in 1998 JIEP Roadmaps
The Technology Roadmap for Electronic Packaging Technology in Japan (1999 – 2010) English version September 1998,translated by SEMI EIAJ / (JIETA – Japan Electronics and Information Technology Industries Association) Report on Semiconductor Packaging Technologies,December 1996
Multi Media Vision 2005,March 1997 Report on MCM / KND Packaging Technologies,October 1997 In 1999 Japanese technologists decided to go to “JISSO”. JISSO is a made up word that means the total system integration. It
encompasses all relevant technologies,such as semiconductor ICs and their packages,other electronic components,PWB,materials,interconnecting structures,environmental protection,and system design.
This was a major decision on the part of the Japanese technology organizations. In 1999 and again in 2001 and 2003 there
has been a JISSO technology roadmap.
The first JISSO roadmap was published in 1999. The Japanese version was published in August 1999 and an English version followed in September 2000. The second JISSO roadmap was then published in April of 2001. This roadmap was also published in English. The 2003 JISSO roadmap was only published in Japanese.

Author(s)
Henry H. Utsunomiya
Resource Type
Technical Paper
Event
IPC APEX EXPO 2005