The debate on the effect of voiding on BGA reliability has continued for years. Many PWB assemblers strive to minimize
voiding,particularly with the advent of lead-free processing and in fine feature area array devices. Although solder pastes
have been designed to minimize voiding,and processing guidelines exist to mitigate void formation during reflow processing,
the presence of a microvia in a PWB pad can contribute significantly to void formation. It is believed that the depression in
the pad caused by the microvia traps air during the stencil printing process,and the air cannot fully escape during reflow.
A process of filling the vias with copper at the board fabrication phase,thereby eliminating the depression that contributes to
voids,was tested for its effectiveness in void mitigation during assembly. The test compares the voiding results of filled vias
with those of unfilled vias and flat pads with no vias at all. The test vehicle and methods,as well as the results of the tests are
presented and discussed in detail.

Nitrogen inerting has been widely reported to reduce defects in lead-free reflow soldering. However,many solder pastes
available claim that they either do not need nitrogen or work equally well in air. While some of these pastes can produce an
acceptable joint quality,they are very susceptible to any narrowing of the process window and some cannot produce high
quality joints even under the most advantageous conditions.
At a leading consumer electronics manufacturer in Asia,three pastes from major producers were compared. Commercial
boards were reflowed in air,and in nitrogen at two purity levels. The boards were then visually inspected for joint quality
using the manufacturer’s standards. The results showed that even the joint quality produced by the best paste could be
improved using nitrogen and the highest nitrogen purity tested could bring the worst paste up to the standard of the best.

(not available)

The industry is in full transition towards lead-free assembly. Due to the different physical,mechanical and chemical
properties of lead-free solder alloys,transitioning lead-free soldering without creating defects or reducing yields has been a
challenge to some.
This paper summarizes the findings coming from customer experiences and details ways these defects may be caused and
how to prevent additional costs due to added repairs or reduction in production yields. The alloys of focus are the popular tinsilver-
copper (SAC305); this solder has experienced the most use in the industry at this time.
The present experiences with lead-free solders seem to indicate that a properly selected alloy,flux chemistry,equipment
selection and process optimization can give reliable assemblies with lead-free SAC. This paper will focus on the SMT
process although similar analysis has been done at the customer level with wave,selective and hand-assembly.

Although in Europe and North America wave soldering is widely regarded as a process that is being rendered obsolete by reflow processes the proliferation of electronic circuitry has more than compensated for that trend. The reality is that globally there are probably more wave soldering machines in operation now than there have ever been. Wave soldering provides a reliable method of affecting a large number of joints quickly and cost effectively and can handle a wide range of surface mount as well as through whole components. With good equipment,good soldering materials and a printed board assembly properly designed for wave soldering zero defects is a realistically achievable target. Because the 2001 legislation that drove the move to lead free in the Japanese market was directed at consumer electronics where wave soldering was the dominant assembly method experience with the process extends back to 1999. In the seven years since mass production by lead-free wave soldering began,and as the number of lead-free lines in operation grew to the thousands a considerable database of experience has been accumulated. Although regarded as a simple process compared with reflow soldering wave soldering has its own unique set of challenges. One distinguishing feature of the process is,for example,the need to manage up to 1000 lb of molten solder and that has economic as well as technical considerations. In this paper the authors report the lesson’s learned during company’s experience of wave soldering in commercial mass production since 1999 and explain how the data collected can be applied to the design and operation of wave soldering equipment and the assemblies soldered on that equipment to achieve reliable solder joints cost effectively.

There are various C4 (Controlled Collapse Chip Connection) solder bumping technologies used in volume production. These
include electroplating,solder paste printing,evaporation and the direct attach of preformed solder spheres. FlipChip in
Package (FCiP) demands many small bumps on tight pitch whereas Wafer Level Chip Scale Package (WLCSP) typically
requires much larger solder bumps. All these technologies have limitations for fine pitch bumping. The most commonly used
method of generating fine-pitch solder bumps is by electroplating the solder. This process can be costly,especially when it
comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to
grant exemptions from the ban of lead in certain solder bumping applications. However,the second level assembly cost of
Lead-Free and Leaded line in parallel is driving for a commonality to move to lead-free for the entire industry.
The terminal metals process forms C4 (Controlled Collapse Chip Connection) solder bumps and the associated bump limiting
metallurgy pads on the surface of silicon integrated circuit wafers. The Bump Limiting Metallurgy (BLM) or Under Bump
Mettalurgy (UBM) pads are located between each solder bump and the surface of the wafer. Typically,the wafers contain a
replicating pattern of chips / die. The UBM and C4 solder bumps provide an electrical and mechanical connection for the
chip to its first level package
C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec.
C4NP addresses the limitations of existing bumping technologies by enabling low-cost,fine pitch bumping using a variety of
solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass
templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm
(or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy
selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both,finepitch
FC in package as well as large pitch / large ball WLCSP bumping applications.
This paper provides a summary of manufacturing and reliability results of C4NP Lead-Free bumps and compares it with the
Electroplated High Lead solder bumped high-end logic devices. We also discuss the relevant process equipment technology
and the requirements to run a HVM (high volume manufacturing) C4NP process. We will also describe the C4NP
manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is
provided by IBM’s packaging operation at the Hudson Valley Research Park in East Fishkill,NY

A designed experiment evaluated the influence of several variables on visual appearance and strength of Pb-free solder joints.
Components,with leads finished with nickel-palladium-gold (NiPdAu),were used from Texas Instruments (TI) and two
other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed
wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electroless Ni/immersion Au),reflow
atmosphere,reflow temperature,Pd thickness in the NiPdAu finish,and thermal aging. Height of solder wetting to
component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a
“lead pull” test determined the maximum force needed to pull the component lead from the PWB.
This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have
the greatest contribution to the heights of lead side wetting. Reflow temperature,palladium thickness,and preconditioning
had very little impact on side wetting height. For lead pull,variance in the data was relatively small and the factors tested
had little impact on lead pull results.

New ROHS standards are forcing the electronics industry to find a replacement for leaded surface finishes. Even more
rapidly than the legislative decision to move away from lead,electronics were moving to much smaller,faster and higher
function applications. Not only does the new surface finish have to be lead free but it will have to perform with circuit
designs that are increasingly challenging. A flat,planar surface is an obvious and minimum requirement. Beyond this,a
preferred finish should be simple to apply,consistent in performance,and durable/resistant to aggressive and corrosive
environments.
A final finish that has been able to deliver a planar surface for the solderability of fine components as well as maintain ease of
use for fabricators is immersion silver. In recent years,immersion silver has grown as the final finish of choice for a large
variety of end use applications. Immersion silver has a wide variety of fabrication/manufacturing and functional advantages
over other lead free surface finishes. One shortcoming of immersion silver is its potential to tarnish in sulfur and sulfide
environments. A post treatment has been developed which delivers significant tarnish inhibition to thin silver coatings,
translating to a more robust and corrosion resistant finish. This work investigates and verifies the effectiveness of a tarnish
inhibited coating,with focus on confirming the coating’s compatibility in modern,fine-pitch assembly applications.
Controlled assembly studies focus on wetting characteristics,solder paste compatibility,and bridging risks are discussed.

In order to meet the growing requirement of eliminating lead from electronics,the printed wiring board (PWB) industry is migrating from hot-air-leveled solder (Sn/Pb) to lead free compatible alternative final finishes. Among the available alternatives which include organic solderability preservative (OSP) immersion silver,immersion tin and electroless nickel/immersion gold,the OSP type coating is considered to be one of the leading candidates because of its excellent solderability,ease of processing and low cost.
This paper uses Gas Chromatography-Mass Spectroscopy (GC/MS),Thermogravimetric Analysis (TGA),and X-ray Photoelectron Spectroscopy (XPS) to characterize the relative thermal properties of a novel high temperature (HT) resistant OSP coating. The GC work performed in this study clearly shows the key organic components in the HT OSP coating that affects solderability. The GC work also shows the alkyl benzimidazole-HT used in HT OSP is of the lowest volatility. The accompanying TGA data also illustrates that the HT OSP coatings have a higher decomposition temperature compared to existing industry standard OSP coatings. The XPS shows that HT OSP has only about 1% increase of oxygen content after five lead-free reflow cycles. In combination,these improvements are assessed relative to the industry needs to meet the performance challenges of lead free soldering.

Since the issue of the European Union directive [1] on the restriction of the use of certain hazardous substances in electrical
and electronic equipment (RoHS) and its predecessor WEEE directive [2],the global electronics industry has been actively
interpreting the resulting EU member state regulations,defining responsive business strategies,and implementing the
technical and business processes necessary to meet all facets of these directives. Many companies have allocated significant
resources to ensure that their products can be marketed within the European Union and are now generally in the final
implementation stages of their RoHS compliance strategies.
China is motivated to reap similar environmental benefits for its citizenry and the China Ministry of Information Industry
(MII) is actively drafting its own environmental regulations for Electronic Information Products (EIP). Key elements of
these China environmental regulations may deviate substantially from the EU RoHS directive. Such deviations could pose
severe logistical challenges to the electronics industry.
Known differences to date include the use of government issued labeling requirements for all EIP products and the
mandatory use of government certified product compliance testing prior to market introduction. As well,uncertainty exists
around the use of an EIP catalogue that will define applicability of the China regulations (potentially incorporating products
that are now exempt from EU RoHS). At this time the catalogue does not exist,but efforts are underway to select the
products that will be incorporated. All regulations that require business procedures or unique product attributes over and
above EU RoHS will drive up production costs and increase product introduction cycle times.
This paper describes the requirements of the China MII environmental regulations as currently proposed,comparing and
contrasting the key differences with the EU RoHS directive and highlighting the resulting electronics industry challenges. It
discusses the business consequences of complying with multiple directives and emphasizes the need for convergence of all
global environmental stewardship programs.