The Restriction of Hazardous Substances (RoHS) directive is requires companies to change the way they design,
manufacture,track,and bring new products into the market. In order to provide the necessary controlled processes for RoHS
compliant electronic design and manufacturing,original equipment manufacturers (OEMs) and Electronic Manufacturing and
design Service providers (EMS) must partner to develop product-based strategies. Tactics utilized are customized depending
on the exact end market requirements.

Companies are refining their processes to better ensure their compliance with environmental regulations evolving around the world. These processes reflect internal use models and collaborative processes for obtaining compliance information. Companies are moving from sourcing simple part and material compliance to developing sustainable environmental compliance use models that incorporate due diligence and methods to obtain and analyze critical information. Company approaches to gathering information are evolving to include:
• Direct sourcing of more detailed compliance information (RoHS/WEEE) from suppliers
• Physical lab-based verification to ensure sourced information is consistent and to fill gaps when manufacturers don’t provide the needed information
• Use of in-field X-Ray Fluorescence (XRF) testing to screen parts and materials as they are received to ensure expected material composition
• Methods to monitor worldwide regulations and translate them to business rules used in compliance processes
In the past couple of years,industry organizations and companies have strategized to address compliance regulations such as the development of standards for sourcing material composition content (IPC-1752),standards for certifying products and processes compliance (IECQ),development of tools to manage content and roll-up material content to report at the finished product level,refinement of XRF (X-Ray Fluorescence) to provide in-field testing for hazardous substances.
This presentation helps companies to identify and detail the internal and collaborative environmental compliance use models needed to confidently support regulations with appropriate due diligence. The presentation details types of data and best practical techniques to obtain the crucial information required to drive the use models. It includes a review of material declaration standards,certification standards,testing and their roles in confident due diligence. This session also discusses companies and products considered exempt or out-of-scope from the compliance regulations,such as aerospace and defense companies,and the business and technical impact.
The information presented is based on IHS’ experience with sourcing environmental compliance information and work with industry providers of lab-based and in-field testing solutions. The practical information presented here will have a strong appeal to OEMs and EMS-providers who need to ensure environmental compliance and manage supply chains.

The IPC's Lead Free program addresses one of the 6 Hazardous Substances regulated by the RoHs directive. Certification to the QC 080000,the IECQ HSPM Specification, addresses the other 5 Hazardous Substances called out by RoHS.

The process challenges of lead free wave soldering often require the use of new flux chemistries when compared with the
relatively tolerant tin-lead wave soldering process. In some cases,the fluxes used in tin-lead soldering work well in lead free
assembly. In other cases,however,the complexity of the assemblies dictate more active,heat-sustainable products
formulated specifically for lead free applications.
This paper reviews the J-STD-004 and how it is used in flux categorization and selection. It also discusses the major types of
flux formulations available,and the design,process and reliability implications of using each type. The purpose of the paper
is to help the reader make an informed choice when selecting wave solder fluxes for lead free processing.

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We have developed a new thermosetting polyimide build-up material for high performance build-up PWBs,which can mount
high speed CPUs with high I/O numbers. These PWBs meet the following requirements; good processability for the
fine-pitched circuits,the low dielectric characteristics,and the excellent mechanical properties.
Our proposed polyimide build-up material shows a dielectric constant (Dk) of 3.1 and a dielectric loss (Df) of 0.01 (at 1GHz).
Moreover the material shows following mechanical properties; a low coefficient of thermal expansion (CTE) of 45ppm and a
tensile strength of 100MPa. Even though the material has a low surface roughness Ra of less than 200n meters,we have
successfully deposited an electro-less plated copper layer with very high peel strength. This means that the material is
suitable for fabricating fine-pitched circuits,even when using a conventional semi-additive process. Actually,we could make
a fine-pitched circuit of less than 10micron L/S (Line and Space).

As a promising candidate for future substrate with high pin-count and low transmission loss at high frequency,we have
developed an all polyimide multi-layered board laminated by single batch process. Compared with circuit boards of glassepoxy
and ceramics,this circuit board made from polyimide films is thin and decreases transmission loss. It makes wiringdensity
higher and manufacturing cost lower,because of having all-layer IVH,Inner Via Hole,structure fabricated by single
batch process. It is a significant feature that the process applies new interconnection technology to formation of conductive
paste via in polyimide films,by laser-drilling and screen printing. By the most suitable condition of paste volume,
temperature and pressure in laminating process,we have achieved 1.0 milli-ohms in resistance for each via.

A Design of Experiment (DOE) was conducted to determine the best filler,or combination of fillers that would offer the best
reduction of CTE expansion from 50oC to 260o C without compromising electrical,chemical,mechanical or thermal
performance of the base Polyimide resin. Our study here shows that a unique combination of fillers can reduce the percent zaxis
expansion of a V0 Polyimide from 1.45% total expansion to 1.28% better than any single type of filler. Thus offering
higher reliability in Printed Wiring Board (PWB) applications that continuously operate in conditions of severe thermal
cycling.

This newly developed material and process enable the manufacturing,using a single pressing process,of multi-layer circuit
boards with inner via-holes in every layer. Because this material utilizes conventional circuit board materials for its structural
components,it not only provides proven high reliability and ease of circuit assembly,but also offers a short lead-time and high
production yield due to adoption of the following processes used during the manufacture of conventional printed circuit boards.
§ Use of a mu lti-layer substrate consisting of copper foil,glass-cloth-based insulation layer,adhesive layer,and cover film
§ Application of an etching process to the copper foil to produce a fine-patterned circuit
§ Generation of blind via -holes using laser processing and hole cleaning
§ Formation of via-bumps by filling metal-based paste and removing the cover film
§ A multi-layer circuit board with inner via-holes in all layers can be produced by aligning the insulation layers and pressing
them together in a single operation.
The materials used in this process require a variety of key technologies that enable laser processing,dimensional control,
conductive paste filling etc. This paper describes these techniques and includes an example of the production of a multi-layer
circuit board in a single pressing operation,followed by reliability evaluation results for the whole circuit board.

The trends of increased functionality and reduced size of portable wireless products,such as handsets; PDAs are demanding
increased routing densities for printed circuit boards. The handheld wireless product market place demands products that are
small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld wireless phones
with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with smallest,lowcost
technology.
Historically,the industry has met this challenge through high density interconnect technology and increased silicon
integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology,is
one method for constructing circuit boards with high routing density demands.1
For HDI board,vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF),using processing
techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper/electrolytic plating.
The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher
routing density,lower metal count,reduced board area and increased functionality as compared to conventional boards. HDI
improves the wiring density by using build up microvias in the outer layers. However there is still dead space where
components cannot be mounted and lines cannot be wired,because of staggered via hole structure.
On the other hand,ALIVH-G (Any Layer Interstitial via Hole) needs no through hole. This is because any two layers are
electrically connected by IVH (Interstitial via Hole). The IVH can be placed in any position. Since there is no through hole
that disturbs interconnections between components,the dead space becomes reduced and the wiring capability is improved
greatly.2
Past board technologies used stacked microvias on the outer layers. Current board designs use ALIVH-G technology. These
vias are laser drilled and the interconnection technology used is conductive copper paste. The typical design rule is
Lines/Space 100/100 micron and Via /Land is 200/400 microns. ALIVH-G technology makes a lightweight substrate (less
than 100g)
The paper presents the evaluation conducted to ensure the stability of the laminate and microvias through the double sided
reflow process. This was evaluated as a part of the phone product qualification build.