Constitutive and failure descriptions of SnAgCu solder alloys are of great interest at the present. Commonly,constitutive models that have been successfully used in the past for Sn-Pb solders are used
to describe the behavior of SnAgCu solder alloys. Two issues in the characterization of lead-free solders demand careful attention: (i) Lead-free solders show significantly different creep strain
evolution with time,stress and temperature and (ii) The building of valid constitutive models from test data derived from tests on solder joints must de-convolute the effects of joint geometry and its influence on stress heterogeneity. In the first part of the talk I will review the common approaches to modeling solder behavior,along with their limitations and then describe our efforts in developing constitutive models of SnAgCu solders that are valid across a wide range of strain rates.
The problem of solder joint fatigue is essentially one of fatigue crack growth. However,there is little work that has been done to arrive at fatigue life estimations by means of tracking of the crack front and its growth. Common fatigue life models such as the Coffin-Manson rule are empirical and therefore,limited in their applicability and in the insight they provide. There are several challenges to employing a fracture mechanics approach to accurately track the growth of a fatigue crack in a solder joint. Key
among these,are the facts that the problem involves large-scale yielding,viscoplastic solder behavior and complex geometries. In the second part of the talk,I will describe the various approaches to
modeling solder joint fatigue and present our efforts at developing Cohesive Zone Model inspired approaches to predicting crack propagation at solder interfaces.

For many of the Pb-free solders required under the European RoHS directive,there is now sufficient information,primarily in the form of the results of accelerated thermal cycling of various levels of severity,to develop acceleration models for the creep-fatigue of these solders. In this paper the parameters for the SAC405/305,SAC205,SAC105 and SnAg to replace the parameters for eutectic SnPb in the well-established Engelmaier-Wild solder creep-fatigue model.

Due to In-Circuit Test issues probing difficult to penetrate processes such as Pb-free solder,OSP (Organic Solderability
Preservative),Immersion Au (Gold),Ag (Silver),Sn (Tin) and No-Clean,as well as the different manufacturing process
variations like wave,select wave and reflow (single and double),new innovative razor sharp probe tip styles were developed
(Figure 1). It was determined that a probe tip that has the qualities of a sharp blade edge would help to penetrate these problem processes. Edge sharpness has been determined to be a critical factor in the successful penetration of these processes within via and test pad applications. In addition,due to the sharpness of the edge,the penetration is effective even off center of the test via or in the pad area as well. Most tips used to probe vias today contain a single point design with the mentality that this sharp single point will break thru these board processes/contaminants. However,in most cases a single point probe will bottom out in the pool of flux contained within the via resulting in poor electrical contact. A razor sharp tip style will better penetrate these hard to probe fluxes and contaminants without bottoming out. Typically,Test Engineers
would be forced to increase the probe spring force to break-through these contaminants,but high-density PCB’s do not allow
the use of higher spring forces due to the increased possibility of board flex which can cause damage to expensive boards. The use of the razor sharp probes does not require a higher spring force and in some cases the spring force can be reduced. Because of these innovative tip styles,first pass yields are significantly increased,repeated fixture actuations are not needed,false failure rates and NDF’s (No Defects Found) are reduced,all of which results in less test time and faster board throughput which ultimately lowers board test costs.

All but the most simple circuit boards processed in recent times are inspected using in-circuit testing,ICT. In order to test on pads or connections printed with no-clean solder paste; the post-reflow flux residue must be easily penetrated by ICT pin-probes. Additionally,the electronics industry continues to move from tin-lead solder alloys to various lead-free alloys,particularly the tin-silver-copper alloys that usually require hotter reflow profiles. The hotter reflow conditions required for lead-free solder paste influence the consistency of the solder paste flux’s residue and its suitability for in-circuit testing,often producing a hard,brittle residue that is difficult to pin probe.
A new method of evaluating solder paste flux residue penetrability has been developed. Because most circuit assembly plants use vacuum actuated fixtures,this method uses a common,multi-probe ICT fixture,modified and wired so the probe-to-pad resistance can be evaluated using a very sensitive 4-wire resistance measurement. This method allows measurement of resistances as low as 30 mO?. Four probe forces,three tip shapes and two probe densities have been incorporated into the fixture,so the optimum probe shape and minimum force required to successfully penetrate the solder paste’s residue can be determined. Results are presented for the ICT probe penetrability of the flux residue of several different solder pastes after being processed with different reflow conditions.

Batch cleaning of electronic assemblies is popular in all regions of the world and continues to grow due to its flexibility,ease-of-use and economic considerations. Batch spray-in-air processes tend to dominate the new systems being installed in North America while batch immersion with and without ultrasonics are popular in Asia. In Europe,batch vapor degreasing and co-solvent processes remain quite popular. Regional preferences,local environmental regulations,economics and availability are some of the factors influencing process choice. This study was undertaken to compare the relative performance of each of these processes in cleaning flux residues from underneath low stand-off components. Pros and cons
of each of these processes are highlighted.

Implementation of lead-free soldering technology has created new interest in high performance cleaning of printed circuit assemblies (PCAs). Many studies have been commissioned regarding removal of flux residues from tight spaces; the effect of impact force on penetration; capillary action versus surface tension; and optimization of the pressure/flow balance in the wash module. Little attention,however,has been paid to the prewash section of an inline cleaner. The prewash is a key functional process in successful cleaning during which chemical reactions are initiated,PCA temperature is raised,and gross contaminants are flushed from the board. Traditionally,fan-type nozzles have been used in the prewash. The small droplets produced by fan nozzles are indeed effective at wetting open surface areas. However,since mass is a critical component of both force (mass x acceleration) and kinetic energy (1/2mass x velocity2),they produce inherently low impact force due to their small size. This limits the ability of fan nozzles to break apart residue and to distribute wash chemistry beneath components on the board surface after initial impact. To address these issues,oscillating nozzle technology has been
developed. These nozzles move the fluid stream back and forth providing a more effective spray pattern in terms of both coverage and impingement. The larger droplet size has more mass and increased impact force,enabling the nozzle to achieve better results at lower pressure with reduced water usage.

During the last 5 years,the processes to remove flux residues especially for lead-free and challenging geometries have demonstrated new cleaning obstacles which have to be overcome.i A new methodology has been recently developed to further increase the propensity for successful cleaning.ii At the core of this method is the thermal identification of the residue matrix. Thermal energy changes the physical state,i.e. transitions between liquid,solid and gas phases. By taking advantage of such specific information during phase transitions,the cleaning process can be tailored to such settings,which in turn increases the cleaning success significantly.
Thermodynamic data from differential scanning calorimetry (DSC)iii will be presented in conjunction with experimental data obtained from subsequent cleaning trials in spray-in-air batch cleaning systems. Flux systems that were investigated during this initial study including rosin-based and No-Clean fluxes. A correlation between phase transition temperatures of reflowed flux residues and optimized cleaning parameters for each flux will be presented.
This approach is revolutionary in that it offers completely new,previously untapped avenues to clean challenging electronic assemblies. It also offers insight to previously set process limitations on process temperatures that might have to be reconsidered.

This paper is focused on the impact of solder hole fill on the reliability of the plated-through-hole (PTH) solder joints with different board thicknesses. Finite element analysis (FEA) is employed to understand the strain and stress of copper and solder with various solder fill percentages. The FEA prediction on fatigue life of copper barrel and solder joints are compared with experimental results,and the role of the pin wetted length (PWL) in PTH solder joint reliability is discussed in detail.

Flip chip bonding is the most desirable direct chip attachment approach for minimizing electronic assembly size as well as
improving device performance. For most prototyping applications it is not cost-effective to purchase individual integrated circuits (ICs) that are solder-bumped as this typically requires the purchase of entire wafer. Also,many unpackaged IC’s in die form are not available for purchase as an entire wafer for subsequent solder bumping. As an alternative to solder bumping,manufacturers
of wire bond equipment have developed the gold stud bump process which allows single IC’s to be automatically bumped using
1-mil gold wire. However,the rapid formation of brittle aluminum-gold (Al-Au) intermetallics at elevated temperatures (>200oC) precludes the use of thermocompression flip chip bonding due to the unreliability of the bond at the IC pad interface. To overcome the intermetallic problem at the ICs aluminum-metallized bonding pads,an electroless nickel and gold plating process was developed for making a gold-bondable diffusion barrier for use on individual,unpackaged silicon IC’s. This process
provided an electroless gold layer suitable for accepting the gold wire stud bumps as well as providing the necessary barrier to Al-
Au intermetallic formation. A number of experiments were conducted using electroless nickel of various phosphorus contents to determine which would provide an optimal diffusion layer. Data will be presented comparing immersion and autocatalytic gold
plating processes. Test wafers were stud-bumped and exposed to accelerated temperatures then shear tested. Electroless nickel,
immersion and autocatalytic gold plating process parameters were optimized to provide high reliability interconnections when using the high temperature thermocompression flip-chip bonding die-attach method.

During the process from wafer fabrication to completing the final plastic package there are a number of upstream processes that negatively impact subsequent operations. Problems at wirebond can be traced directly to both fab and saw operations. Analysis of bond pads from the fab reveal traces of flourine that can lead to the formation of HF which is highly corrosive to aluminum and some passivation materials. Most post fab processing operations such as test maintain high humidity levels to minimize ESD/EOS damage to the die. The same high moisture level conditions that are required to minimize ESD/EOS damage supply the necessary moisture to cause trace halogens to form HF causing further corrosion on the bond pads.
Provided with an infinite source of H2O,the flourine becomes a reactive ion that seeks aluminum to form aluminum fluorides. In this reaction the halogen ion is liberated and OH ions in the water reacts with Al to form Al (OH)x and then AlOF. Some of the AlOF becomes AlO and frees the F to become HF. The halogen can now react with a new aluminum atom to repeat the process forming layers up to hundreds of angstroms thick. To terminate the process the flourine has to be eliminated else wire bond ends up with a bond pad that is both difficult to process and can lead to long term reliability issues.
This paper discusses how to remove those halogens,eliminate saw corrosion and improve wirebonding without the use of legacy argon plasma solutions which only serve to redeposit both detectable carbon and halogen elsewhere on the wafer/die. This process also demonstrates a solution that is less than a “milli-penny” per die compared with the expensive and unreliable argon plasma. Results to date have shown that not only can corrosion be eliminated at saw but the die received at wirebond has a thinner oxide layer than material leaving the fab (~20A).