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The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small,and
focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield. Multiple lamination cycles,the indeterminate yield of sub-cores,backdrilling and extended plating times add to the overall poor yield of high layer count PCBs. An attractive solution to the high-aspect-ratio PTH dilemma is to break the high-layer-count PCB into a number of subassemblies that can be 100% inspected and then be interconnected. Conductive paste-based interconnects are an attractive interconnect technology option,but passively loaded copper or silver filled pastes do not demonstrate the requisite performance and reliability. Sintering conductive pastes,which metallurgically bond directly to the copper pads of the PCB during a standard lamination cycle,do meet the requirements of these high-layer-count PCBs and at substantially lower cost than conventional manufacturing methods.

This paper presents systematic investigations on complete Through Hole filling for cores by a Cu electroplating process as an alternative to the common paste plugging process. This electro plating process consists of two steps,a first process to merge both centers of the through hole walls (X- plating) followed by filling up the resulting Blind Micro Vias. Processes and manufacturing technology are described as well as current limitations and requirements. Complete filling of through holes is achieved by Reversed Pulse Plating,RPP. This Through Hole filling technology is targeting both at HDI production and also at the packaging level.
Through Hole filling by RPP offers a viable alternative to the standard paste plugging for core processing in substrate manufacturing. Current core manufacturing requires a paste plugging process for through holes so that subsequent build up layers can be produced by sequential lamination,the flat core surface is essential for stacked via and also via in pad technology.
This paste plugging process requires additional process steps,each of which has its own limitations and contributes to the overall cost. Filling the core through vias by electroplating can eliminate the plugging process and significantly reduces the number of overall process steps which will also reduce costs. Moreover,it offers certain advantages such as potentially higher reliability in accelerated aging tests and an improved thermal management as the thermal conductivity of a completely copper filled through via is significantly higher than a paste plugged through via.
Today’s challenges in the so called Through Hole Filling process are represented by through holes with a high aspect ratio. Voids after X-Plating occur easily for smaller through hole diameter and higher board thickness. In addition,depending on designs,different pitches on one board increase the difficulty to achieve an acceptable plating uniformity. This paper presents systemic variations of some key parameters and concentrates on the performances of the second plating step,the blind micro vias filling. Main focus is laid on recess distribution. Parameters as reverse pulse parameters,inorganic concentrations (Cu,Fe,and sulfuric acid),organic concentrations,electrolyte flow and temperature have been systematically varied and their influence on the filling performance are described.

Miniaturization and increased functionality demands of electronics have substantially decreased the sizes of electronic features that need to be plated. The circuit density of printed circuit designs has been increasing accordingly. Copper is the most preferable metal used in electronic industry for filling small features due to its electrical and thermal conductivity properties and the possibility of electroplating. New technologies started to develop in order to completely fill through vias in build-up core layers in HDI and IC with solid copper. This has been associated with improved thermal and mechanical properties as well as with increased reliability. In this paper the effect of the chemical composition and the processing parameters on the hole filling characteristics of copper electroplating has been studied. It was established that a preliminary treatment in a chemical solution was the most significant factor for void free filling of blind micro vias. Copper concentration was also significant factor,while the leveler concentration was only significant in some cases. The brightener concentration was not a significant factor for the responses tested,which included the fill ratio,dimple,planarization,and surface copper thickness. The optimum conditions of a DC process for filling up a wide range of via sizes and plating simultaneously though holes were determined. The results obtained allow for enhancing via plating capabilities and increasing the reliability. The second part of this paper shows a novel process for filling through vias in core layers up to 400 mkm thick. This process includes two subsequent steps,being PPR or DC plating depending on the substrate thickness and hole diameters. The through vias were completely filled by using a modified process for acid copper electroplating. The chemical and plating parameters are discussed in the paper. Data enclosed demonstrate through vias in build-up core filled without any voids and defects. This innovative technology is at an early stage being at the process of further optimization to enable a variety of HDI and IC substrate package designs.

Quad Flat Pack No Leads (QFNs) are thermally enhanced plastic packages that use conventional copper leadframe with wire bonded interconnects. . These leadless components provide an advanced packaging solution that reduces board real estate,with improved electrical and thermal performance over traditional leaded packages. The move towards finer pitch is resulting in using flip chip bumps as interconnects on an interposer substrate and packaging as QFN. [1]
The QFN devices commonly known as BTC (bottom terminated components) are attractive due to their low cost per I/O,performance and low profile; they are also a challenge for assembly due to their low to zero standoff height. Successful assembly yields and solder joint reliability requires careful selection of substrate materials,fluxes,component plating finishes,controlled reflow processes and flatness of package and PWB. [2]
This challenge is enhanced with the transition to lead free reflow as the higher peak reflow temperatures results in more thermal and CTE mismatch between package and PWB. Wire bonded leadframe packages are typically plated with 100% Matte tin or NiPdgold on the solderable terminations. Interposer substrate is typically plated with Electroless nickel /gold for solderability of terminations. War page characteristics of interposer substrates have to be evaluated to minimize stress on the flip chip bumps.
Reflowing packages with flip chip bump interconnects requires a good balance of substrate /package material sets and controlled reflow profiles to ensure proper melt of the bump interconnects and solder joint reliability thru subsequent reflow processes at assembly facilities.
The paper reviews the qualification efforts for solder interconnects on interposer substrates,X-ray and X-sectional analysis of packages and process optimization efforts to improve reliability of the interconnects

Solid tantalum capacitors were introduced to the market more than five decades ago and continue to be widely used. Reliability issues arise when tantalum capacitors are exposed to excessive thermo-mechanical or electrical stresses. While the failure modes and mechanisms due to each of the stresses,thermo-mechanical or electrical,are well researched,the failure mechanics of tantalum capacitors being subjected to simultaneous voltage stressing at elevated temperature have not been thoroughly examined yet.
This paper investigates the degradation of tantalum capacitors under simultaneous thermo-mechanical and electrical stresses. Tantalum capacitors with MnO2 electrodes from two different vendors were examined at an elevated temperature and voltage step stress conditions. Electrical characterization prior to and after the tests was performed to identify degradation and indicators of reliability of the parts. Additionally,destructive and non-destructive failure analysis was performed on virgin and stressed samples.
The results revealed degradation and breakdown of the dielectric as the relevant failure mechanism due to thermo-mechanical and electrical stresses. This knowledge provides a better understanding of the possible reliability risks experienced in the field and may help in the development of screening or qualification tests to address these risks.

- Hot nitrogen technology for local inerting system of wave
soldering machines has proved to give significant advantages with Tin Lead or Lead free solders:
- Better heat transfer on the PCBs,especially between the 2
waves (very important for lead free)
- Longer equivalent contact time (up to +60% for massive
components),allowing a higher conveyor speed
- Better soldering quality,less joints defects: average -40% (up to
-80% in some cases)
- Almost maintenance-free system: no solder clogging and no flux vapors residues on the N2 diffusers (cleaning effect)

As the use of lead-free alloys has increased in electronic assemblies,much work has been done to develop Design for Manufacturability (DFM) guidelines for the new materials. However,there are still some challenges remaining with wave solder,which is a complex process with many interacting factors. One such challenge is achieving good Pin Through Hole (PTH) barrel fill on thicker PCBs,particularly for power/ground pins connected to multiple plane layers. One important factor in the selective wave solder process is the size of the selective pallet opening around the PTH pins. It has been observed that larger pallet openings generally provide better barrel fill than smaller ones,but further research is needed to determine the recommended pallet opening for more thermally challenging product designs. The recommended pallet opening can then be used to determine DFM guidelines for the component keep out from the PTH pins on the solder side of the board.
This paper presents the outcome of a study done with a thick,thermally challenging test vehicle wave soldered using a wide range of selective pallet opening sizes. The test vehicle is 3.05mm (0.120”) thick with twenty copper layers,including ten plane layers,and is populated with several PTH component types. Other design variables include pin to hole clearance,and quantity of plane layers connected to each pin. The PCBs were assembled with a Pb-free alloy (Sn-Ag-Cu) and also SnPb as a baseline. In the first part of the investigation,a Design of Experiment was performed to optimize the wave solder process parameters and in the second phase,the optimized process parameters were held constant to focus on varying the pallet opening size only. The results for the various pallet opening sizes and their interaction with the other design factors will be discussed.

Bottom terminated component (BTC) assembly has rapidly increased in recent years. This type of package is attractive due to its low cost and good functional performance (improved signal speeds and good thermal performance). However,it creates many challenges to the assembly process and post assembly inspection.
This paper discusses the design,assembly process and inspection challenges of bottom terminated components. The study considers many factors,including design variables (solder mask defined pad,non solder mask defined pad,mixed pad design,different via design,thermal connection,orientation,etc.),process variables (stencil design,reflow profile,reflow atmosphere,etc.),board surface finish variables (OSP,I-Ag,ENIG) and fabrication variables (solder mask thickness and type).
Keywords: bottom terminated component (BTC),quad flat no lead (QFN) package,land grid array (LGA) package,micro lead-frame (MLF) package,void,solder,SMT,lead-free.

The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi,Sn57.6Bi0.4Ag,Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies,reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi,Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.