The increased temperatures associated with lead free processes have produced significant challenges for PWB laminates.
Newly developed laminates have different curing processes,are commonly filled with ceramic particles or micro-clays and
can have higher Tg values. These changes designed to reduce Z-axis expansion and improve the materials resistance to
thermal excursions through primary attach and rework operations have also produced harder resin systems with reduced
fracture toughness.
Celestica has undertaken an extensive “Spherical Bend Test” program to assess lead (Pb) free compatible materials and area
array packages. This work has confirmed “Pad crater / Pad Lift” as the dominant failure mode in Pb-free materials in
agreement with observations from multiple streams of field returned product. This work discusses the multiple phases of
testing and the implications for mechanical reliability of Pb-free product. The initial phase was designed to confirm or refute
the established relationship between strain rate and safe working strain in Pb-free materials. The second phase studied the
effect of extended thermal excursions for an extensively used standard loss laminate material. The third phase was designed
to directly compare standard loss laminate materials and has confirmed the impact of filled resin systems identified by other
investigators
This new work seems to confirm the relationship between board thickness and safe working strain established by in
IPC/JEDEC-9704: “Printed Wiring Board Strain Gage Test Publication”. Data is only available for a limited number of
package designs but these selected packages are believed to generate conservative strain limits for manufacturing process
guidelines. The design of the most recent test plan was intended to generate data that would allow investigators to generalize
the effect of package compliance on the safe working strain of the assembly by correlation of test data from multiple
packages to an existing simplified mechanical model.
Assembly processing,test methods and results will be documented in addition to discussion on resultant data,failure
analysis,distribution parameters. The effectiveness and predictive range possible from the simplified model will also be
discussed.

As technology advances,understanding thermal management issues of high frequency PCB’s increases. There are many different aspects to consider for PCB thermal management. This paper will investigate thermal management issues of high
frequency PCB’s as it relates to material properties,insertion loss and circuit design configurations. It will be shown that
there are many tradeoffs between these aspects which can be very beneficial for the circuit designer to be aware of.

With the emergence of high speed,controlled impedance circuits requiring increasingly tight tolerances,there is a realization among designers and fabricators that more precise data is needed than the normal “data sheet” information given by materials companies. To meet this need,an extensive study has been conducted over the past year to closely evaluate flexible circuits in “real world” transmission line structures. The outputs of this study are clearly understood impedance and loss data that can be used as a basis for designs and fabricated structures.
The following structures will be evaluated:
-Microstrip Lines
-Covered Microstrip Lines
-Microstrip Lines with ENIG Finish
The following materials will be evaluated:
-Standard FR4 (100 um thick),Mid-Grade Glass Reinforced Epoxy (100 um and 50 um thick) and Low Loss Rigid Glass Reinforced Epoxy (100 um and 56 um thick)
-Adhesiveless Polyimide (50 um and 100 um thick)
-Fluoropolymer/Polyimide Composite (50 um,75 um and 100 um thick)
Loss will be evaluated in terms of loss per unit length versus frequency at frequencies between 0.2 GHz to 25 GHz for long lengths. Impedance is measured utilizing typical TDR systems used by fabricators and compared to commercially available impedance calculation systems.

Creep corrosion normally happens in the end system,PCB,connectors and components are widely noted due to the exposure of
high sulfur environments under elevated humidity. In this study,the major focus is the investigation of PCBs with 3 different
types of surface finish (ImAg,Post-Treatment ImAg,HT-OSP),SMD vs NSMD and non clean organic acid flux residue from
simulating wave soldering process under MFG Test (Mixed Flowing Gas Test). The realistic mixed flowing gas (H2S,SO2,NO2,
Cl2) at certain concentration of each and relative humidity are designed to accelerate creep corrosion happening.
One of the purposes in this study is to investigate the effect of the mixed flowing gas with various H2S concentration (500 ppb,
1000 ppb,1700 ppb) at 5 days duration on the corrosion rate (nm/day) in the Cu coupon and Ag coupon in order to understand
how H2S drives the corrosion acceleration. The data are also verified by the methods of Weight Gain Analysis and X-Section
with SEM/EDX.
The result shows much higher corrosion rates are observed on Cu coupon in both Individual and Mixed Flowing Gas Tests. The
corrosion rate of Cu coupon rapidly increases with H2S concentration above 1000 ppb. Ag coupon have more active corrosion in
low H2S concentration than high H2S concentration. Flaking corrosion also happens on the Cu coupon with heavy corrosion
product in the high H2S concentration test condition. And more visible creep corrosion is observed on HT-OSP finished circuit
boards and SMD,as the residue of organic acid flux residue is not able to prevent corrosion occurrence.

Corrosion resistance is becoming one of the most important topics in the electronics industry. Corrosion results in field
failures and huge losses,which annually total several billion U.S. dollars. The actual extent of losses caused by corrosion is
not well documented in the industry. As such,corrosion is currently one of the most challenging topics and is acquiring
more attention as a result of increased product warranties,new materials and process changes caused by recent legislation
impacting the electronics industry.
Another factor is that the industry used in the past the lead containing surface finish “Hot Air Solder Leveling” (HASL) in
very large volumes. This surface finish does have a superior corrosion resistance because of the Copper/Tin IMC and the
corrosion resistance of the tin surface itself. Therefore corrosion resistance was for a long time no topic for the applications
using HASL. But since the RoHS legislation came in effect in July 2006 and the use of lead containing HASL was restricted,
the industry has looked into and qualified new alternative lead-free surface finishes. Furthermore the lead-free version of
HASL shows some major disadvantages like uneven deposition thickness and as a higher working temperature is needed,a
detrimental impact on the base material cannot be avoided. Companies do expect from these new alternative surface finishes
to show the same corrosion resistance like HASL but many missed to investigate these alternatives concerning their
corrosion resistance performance in combination with their applications. It only came to the attention of the electronics
Industry as they were recently confronted with more and more field failures due to corrosion.
Depending on the final application and the environment to which the product is exposed,the requirements for corrosion
resistance can be significantly different. Products used in military,automotive and medical applications typically demand
higher corrosion resistance than products for lower performance or lifetime expectations,such as consumer electronics or
similar products used in non-aggressive environments. As a result,to avoid corrosion on electronic products each industry
sector has essentially adopted its own reliability testing procedures and standards. These facts all lead to the question,
“What is the right corrosion resistance level of the surface finish for a particular product?”
One key function of surface finishes on printed wiring boards (PWB) is the protection of the underlying metal surface from
environmental influences until assembly operations,such as soldering or wire-bonding,are performed. Also,after assembly
there are areas on the PWB that are not covered by solder,including contact pads,test pads,heat seal and heat sink areas
and the inside of through holes and vias. These areas are covered only by the surface finish and must still be resistant
against any corrosive environment in the field. When corrosion occurs on a surface finish the metal decays and undefined
corrosion products are created. The result of this process could be either an “open”,caused by attack of the underlying
copper or a “short”,caused by creep from undefined corrosion products.
This paper investigates the performance of seven primary types of surface finishes using four different corrosion tests. The
compiled data,findings and recommendations are offered as a guide to selecting the most suitable surface finish based on the
end use application and required level of corrosion resistance.

Testing DDR memories on Printed Circuit Boards has steadily gotten more difficult. Most such memories do not have any on-chip Design-for-Test features. Adequate test access is a disappearing luxury. It is a challenge to present these memories with the critically timed protocols they require to work at all,and,to participate in their test. While Boundary Scan technology (in the memory controller devices) can assist with the access problem,it is increasingly difficult to achieve the required protocols in the serialized environment of Boundary Scan.
DDR memory vendors have been loath to provide on-chip test assistance (DFT),but one example of a graphical RAM with DFT does exist. There is also a newly published IEEE Standard 1581 that offers a way to add DFT to RAM devices,with or without adding new pins to the device. These capabilities dramatically reduce the difficulty in creating stable,reliable,repeatable tests for DDR memories at board test.
The presentation will include a discussion of the DDR memory challenges we see today,and how the adoption of DFT capabilities pays off in higher test coverage,better diagnostics and reduced programming/support time.

Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled,un-powered,vectorless in-circuit test techniques to identify open pins on ICs and connectors. Unfortunately,faster signals and higher-density printed circuit boards (PCBs) have placed pressures on designers to reduce the number of test pads that provide electrical access for vectorless test techniques.
A powered-up test solution using boundary scan as the stimulus generator and a capacitive sensor plate for detection can address this loss of access. This virtual access method can quickly and effectively identify connectivity defects between boundary scan based ICs and other devices,including non-boundary scan devices,connectors,and sockets that lack physical test access.
This test approach employs a novel set of time domain auto-correlation and cross-correlation algorithms that eliminate many of the restrictions associated with existing frequency domain alternatives. More specifically,this test method does not restrict the operating frequency of the boundary scan’s clock signal (TCK) or the number of scan cells in the boundary scan chain. Analyzing the temporal response of a single event pulse in the time domain by use of matched filtering eliminates the need to generate the narrow range of stimulus frequencies that traditional capacitive sensor plate methods require.
This virtual test method works with any boundary scan device that complies with the IEEE 1149.1,1149.4 or 1149.6 standards. A discussion of this test method as well as recent field data,lessons learned and obstacles overcome while implementing this technique on a high-end computer server product at a high volume production facility are disclosed.

The stencil printing process is one of the most critical processes in the electronic production. Due to the requirement: “faster and smaller” it is necessary to place components with different paste volume close together without regard to solder paste printing. In our days it is no longer possible to control the solder paste volume only by adjustment of the aperture dimensions.
The requirements of solder paste volumes for specific components are realized by different thicknesses of metal sheets in one stencil with so called step stencils. The step-down stencil is required when it is desirable to print fine-pitch devices using a thinner stencil foil,but print other devices using a thicker stencil foil.
The paper presents the innovative technology of step-up and step-down stencils in a laser cutting and laser welding process. The step-up/step-down stencil is a special development for the adjustment of solder paste quantity,fulfilling the needs of placement and soldering. This includes the laser cutting and laser welding process as well as the resulting stencil characteristics and the potential of the printing process. Influencing factors on the printing process for step stencils like squeegee speed,squeegee angle,squeegee pressure,squeegee material,printing direction and distance from the step-edge to the nearest aperture are shown in this paper. A test layout was developed with different step heights and different distances from the nearest apertures to the step-edge to give proposals and guidelines for future designs. The transferred solder paste volume was measured with highly sophisticated systems and the results which are gained in this study allow new design guidelines.
The focus of this paper is on the printing performance of step-up/step-down stencils and the paper ends up with a short outlook on 3D cavity printing.

Considering technological advances in multi-depth cavities in the PCB manufacturing industry,various subtopics have materialized regarding the processing and application of such features in device manufacturing.
In a previous paper the topic of solder paste printing on PCBs on standard SMT equipment and with multiple cavity depths was investigated. The success of solder paste printing is a prerequisite for further assembly and reliability of the entire electronic construct. In this paper we intend to examine the overall manufacturability and subsequently analyze the reliability of multi-depth cavity PCBAs,presupposing the presence of solderable features within these cavities.
The intended methods of evaluation for manufacturability will be the evaluation of solder paste volume (PV) and warpage performance.
The intended methods of evaluation for reliability will be the evaluation of mechanical loading (drop test) and thermal loading (TCT,reflow) on PCBA test vehicles.
The aim of these investigations is to identify any possible criteria of a solderable multi-depth cavity PCB,which may affect manufacturability and/or reliability,and if so to which magnitude. Thus,we expect to locate general and possibly specific advantages and/or limitations of such a product under a standard manufacturing environment.
In an effort to achieve a broader understanding of the entire process and product scope,the participants in the trial are an HDI PCB manufacturer,stencil manufacturer and a global EMS manufacturer.

With the miniaturization of components in the semiconductor industry,the need for specialized solder pastes with finer
powder mesh sizes for package-on-package (PoP) assemblies has become imperative and increasingly more common. As the
powder mesh size decreases (smaller diameter powder),more surface area of powder within the paste is exposed and,
therefore,more susceptible to oxidation. The flux vehicle of the solder paste consequentially has more oxides to remove in
order to allow for proper coalescence to form a good solder joint. The intent of this paper is to evaluate whether the decreased
powder mesh size and increased oxide content of the powder in the PoP pastes affects the voiding performance of the
materials,and to what degree.