The Surface Mount Technology (SMT) industry has been faced with several challenges in the past decades. Two of the most recent ones are RoHS compliant lead-free assembly and the adoption of fine-pitch components assembly processes. Moreover,halogen-free is another new requirement for assembled PCB reliability,environmental and health concerns. All these requirements create fundamental challenges of developing a solder paste to satisfy everything. One of the resolutions for these challenges can be the development of the activator package with the advanced organic chemistry technology.
Serial innovative activator system was developed recently for solder paste flux,tacky flux and liquid flux formulation. This paper will discuss three Type 4 lead-free halogen-free no-clean solder pastes (ROL0) developed based on different innovative activators,which respond to the challenges described above. The printing performance,coalescence,wetting,BGA voiding and head-in-pillow characteristics,are compared and discussed in detail. The testing results show all three pastes with the new activators are fully capable of printing and reflowing 01005 components with different board/device finishes,even in air reflow. They can handle a wide variety of print variables,including print speed,long abandon time and a wide range of temperature and humidity. Post-soldering,the paste offers minimized defects,including head-in-pillow and BGA voiding.

•What is Digital Printing
•Ink Jet Technology
•Printing SM using Ink Jet
- Highlights
- Zero clearance technology
- Product improvements
- PCB shops,end users and designers Benefits

- DD Detector is State of the Art
- Software: Addressing all measurement challenges; Measurement Results for Au,Pd and Ni(P),independent of substrate material
- Traceability and Reproducibility through Reference Standards
- XRF-Instrument considerations
- Comparison of Spectra

Atmospheric dust consists of solids suspended in air. Dust is well known for its complex nature. It normally includes inorganic mineral materials,water soluble salts,organic materials,and a small amount of water. The impact of dust on the reliability of printed circuit board assemblies (PCBAs) is ever-growing,driven by the miniaturization of technology and the increasing un-controlled operating conditions with more dust exposure in telecom and information industries.
A fundamental and systematic study on the impact of dust is needed,since not much research has been done in this area. We started by asking some basic questions on dust. Since dust is always present in the atmosphere,under what conditions is dust a reliability concern for electronics? What are the key characteristics of dust? Are some dust types worse than others: e.g.,dust that is more hydrophilic? Should there be classifications of dust? How will different combinations of dust,voltage,relative humidity (RH),temperature,and other factors affect electronic materials and circuits? This paper presents some results towards answering these questions. We designed a group of experiments using real life dust collected from both indoor and outdoor areas. AC impedance spectroscopy (IS) was employed as the measurement technique for this research. We designed test coupons with adjustable spacing between electrodes and measured their electric properties under different relative humidities. We analyzed aqueous solutions produced from dust samples were using their pH and conductivity. And we further analyzed the compositions of the dust samples. We found that dust had a significant impact on the reliability of PCBA. Relating the test results to the analysis results,indoor dust is more sensitive to the change of relative humidity compared to outdoor dust due to the water soluble salts and particle size. At the same dust deposition density,indoor dust is more susceptible to induce moisture related failure,such as loss of surface insulation resistance,electrochemical migration,and corrosion.

Silicone contamination is known to have a negative impact on assembly processes such as soldering,adhesive bonding,coating,and wire bonding. In particular,silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools,offgassing during cure of silicone paste adhesives,and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (ug/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation.

For the last couple of years,the main concerns regarding the electrical performance of blank PCB boards were impedance and ohmic resistance. Just recently,the need to reduce insertion loss came up in discussions with blank board customers.
One approach to alleviate the issue is the change to a lower loss dielectric material. Hence the percentage of boards that require a lower loss material is increasing significantly.
However,changing to a lower loss material influences PCB cost and in addition may affect the reliability of the boards.
The second way to reduce insertion loss is to minimize the conductor roughness. The roughness is influenced by two factors: the initial roughness of the copper foil (as received) and the treatment of the copper surface prior to lamination (a.k.a the oxide replacement).
Our first investigation,presented at Apex 2011,focused mainly on the influence of a wide variety of oxide replacements. The main focus of this follow on investigation is copper foil quality. Several very low profile and ultra low profile copper foils were investigated in a DOE,together with two types of oxide replacements.
The resulting electrical performance characteristics,like impedance,DC line resistance and insertion loss were evaluated in an ANOVA approach.
The paper describes the test vehicle and the testing methodology and discusses in detail the electrical performance characteristics. The influence of the independent variables on the performance characteristics is presented.
Finally the thermal reliability of the boards built applying different copper foils and oxide replacements was investigated.

Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important.
Currently,there is no method for adequately quantifying roughness of a signal trace or a power/reference plane layer within a finished PCB. The measurement methods currently available can only be applied to the base foil,prior to its incorporation into a finished board,as they require direct access to the surface to be measured. In a PCB,this surface is not directly accessible,as it is encapsulated within the board,and attempting to expose the surface will necessarily damage or destroy both the board and the surface of interest.
This paper describes a method by which the surface roughness of a metal foil or conductor layer within a PCB may be determined from a microsectioned sample of the same. A small,non-functional area,e.g. a corner of the PCB,can be removed,and the surface roughness of the circuit layers can be assessed without impairing the function of the PCB.
In the proposed method,a conductor (a trace or a plane) in the microsectioned sample is first digitally photographed at high magnification. The digital photo obtained is then used as an input to a signal- and image-processing algorithm within a graphical user interface (GUI). The latter automatically computes and returns the surface roughness values of the layer photographed. The tool enables the user to examine the surface textures of the two sides of the conductor independently. In the case of a trace,the composite value of roughness,based on the entire perimeter of the trace cross-section can be calculated.

The latest status of new ED copper foil developments is presented: ultra-flat profile for high speed digital boards and ultra-thin foil for finest pitch applications.
Copper surface roughness has become a significant factor influencing the losses in high speed PCBs,particularly as they move into the 10 GHz range and above. A new base foil has been developed which achieves very smooth surfaces.
The combination of the new base foil types and new fine pitch treatments increases the active surface between copper and resin,providing reliable bond strength to proprietary resin systems used for low loss applications.
Ultra-thin foils down to 2µ have been developed for modified semi-additive technology enabling the PCB producer to achieve finest pitch,down to L/S of 20µ/20µ as required in the latest IC-Packaging generation and for flexible printed circuits.
Combined with a proprietary primer resin coating,these new generations of ultra-low profile foils are designed for both,high speed applications and high density boards by increasing the bond strength on low loss and high TG resin systems.

The PCB industry has advanced significantly in the recent millennium. OEM specifications and requirements have also advanced due to the maturing technologies. With this the requirements of Electrical Test of these higher technology products has advanced as well. Long gone are the “Pin in Hole” technology PCBs now surpassed by the large multilayer,blind/buried and Rigid Flex technologies. For the suppliers of Electrical Test,be it “in-house” or sub-contracted the industry specifications can be confusing,and at times non-comprehensible. The OEMs direct the IPC specification (6012,9252A,AS9100,etc) for their fabrication to the manufacturer but do the OEMs/CMs really understand what they are asking? There are many variables associated with these specifications and requirements to their designated classes regarding Electrical Test. OEMs decide what IPC class they wish their product manufactured due to performance requirements but overlook the electrical requirements associated with those requirements. Manufacturing,plating,etching and all those processes may be within the class requirements they require but they overlook the Electrical Requirements associated with their required IPC class. This paper will outline and define what requirements must be adhered to for the OEM community to truly achieve the IPC class product from the Electrical Test standpoint. This will include the test point optimization matrix,Isolation (shorts) parameters and Continuity (opens) parameters. This paper will also address the IPC Class III/A additional requirements for Aerospace and Military Avionics. The disconnect exists between OEMs understanding the requirements of their specific IPC class design versus the signature that will be presented from their design. This results in many Class III builds failing at Electrical Test.

Functional circuit test (FCT) of circuit boards and end products in a high volume (>1000 units per day) production environment presents challenging technical,logistic and cost obstacles that are usually more complex than those encountered at the inspection (automated optical inspection) and the manufacturing process test step (in-circuit test).
FCT “logistic challenges” are even more significant when there is a variety (high mix) of different circuit types to be tested. It is not uncommon for production lines to routinely have fifty or more active board types,each with a difficult-to-forecast production schedule that must respond to varying customer demand.
The exigencies of high volume production—not to mention the economics—preclude the typical “one-off” functional testers or “product-minus-one” found in many production environments. A “universal test system” is required. However,most “universal testers” are typically large and expensive,where (1) cycle times may be several times longer than the line takt rate,and (2) complex fixturing and UUT connection requirements that are difficult to modify in line further impede throughput.
Developing and maintaining revision control of application test programs for FCT is a further complicating factor in a high product mix environment. The difficulty of developing a practical FCT system to be used in the production line is exacerbated when the tests must include accurate and repeatable measurement of “outlier” electrical parameters such as very low or very high voltages and currents,and/or low level and/or very high frequency RF signals.
We have developed a standardized FCT system architecture,combined with fixturing/UUT interconnection solutions designed for the rigors of a high-mix,high volume production environment,significantly reducing total cost compared to typical custom-designed FCT systems. We have also developed algorithmic programming techniques that have proven useful to minimize overall UUT test time.
We will describe how this architectural and procedural approach meets FCT technical,logistic and economic goals by studying the actual functional test of a high-mix,high volume AC driver product,which has more than 50 distinct variations,built in a volume exceeding one million units per year.
The robustness of our technical test solution will be further illustrated by describing test requirements that included voltage measurements of up to 1200V and current measurements up to 40A.