As the FPGA device technology migrates to 28nm technology node and high performance applications,selecting the right package to meet the customer usability requirements and to achieve product reliability goals becomes important. The paper describes the process used in selecting and qualifying the molded flip-chip BGA for cost effective,high performance 28nm FPGA devices. A collaborative approach in partnership with the assembly manufacturer was employed to develop customer collateral that includes handling; reflow/rework and heat sink attach guidelines for the molded flip-chip BGA package. A
detailed thermal modeling of the package was performed to characterize the thermal performance of the package. In addition,compressive loading characterization,component level and board level reliability tests were carried out to validate
the long term reliability performance of the package in customer use conditions. The results of this study demonstrate that the molded flip-chip BGA package is a cost effective and high reliability solution for 28nm FPGA devices.

In light of the recent technological trends within PCB manufacturing industry,there is an increasing degree of interest in understanding the influence factors of mechanical stress on the durability of mobile devices.
In the past,many papers focused on PCB reliability and the influence factors during drop shock test. In most cases,the potential influence factors in regards to underfill have not been fully investigated. Additionally,there is no clear direction on the influence of the interaction between solder mask inks and underfill systems.
The intent of this paper is to identify an accurate method to predict drop test behavior by understanding the surface tension of both,the solder mask ink and the underfill material. This could become a significant advantage for improving the reliability of the entire electronic construct. In this paper a method has been examined that can be used to subsequently analyze the reliability of the latest mobile device related materials and design.
The prescribed test has been constructed using a cross comparison of pad design,surface finish,solder mask and underfill,measured by drop testing. Based on the resulting data,a method was evaluated to predict and optimize drop test reliability by understanding the surface tension of solder mask and underfill (adhesion).
We are now able to identify specific advantages and limitations for different material combinations,without the need of expensive and time intensive drop tests.
In an effort to achieve a broader understanding of the entire process and product scope,the participants in these trials were an HDI PCB manufacturer (AT&S) and it´s material suppliers.

HALT & HASS technology uses a combination of accelerated stresses to expose product flaws early in the design and manufacturing stages (often at board level),improving product reliability and customer confidence. HALT & HASS will be defined and compared to traditional compliance testing to a pre-written test standard. We will discuss why companies are using HALT & HASS and finding success. The basic steps of HALT & HASS testing will be covered along with some examples of types of defects that can be precipitated and detected during HALT testing.
HALT & HASS is used to uncover many of the weak links inherent to the design and fabrication process of a new product as well as during the production phase to find manufacturing defects that could cause product failures in the field. The types of HALT & HASS chambers available in the market along with the equipment capabilities will be reviewed along with how they used for detection of flaws in design,making the product more rugged and reliable. These capabilities are key to precipitation and detection of product defects.

Many manufacturers employ one or more In-Circuit Test (ICT) systems in their PCB manufacturing facilities to help them detect manufacturing process and component defects. These “bed-of-nails” electrical test systems are highly valued for providing the qualities of simple program generation,high fault coverage,fast test throughput,low false fail rates,and exceptional diagnostic accuracy as compared to other available test and inspection techniques.
Advancements in PCB technologies,along with changing test philosophies and manufacturing business models in recent years have created new and diverse requirements for manufacturers of in-circuit test systems. Particular challenges that ICT manufacturers have had to address include the erosion of test point access in certain product sectors; the progression of ultra-low voltage components; the variable test requirements of different product applications; the varying test philosophies of different market segments and different manufacturing regions; and the demanding throughput requirements of high volume production facilities.
This paper highlights how in-circuit test systems have evolved in recent years to include innovations and advancements to address these challenges and trends. Topics that will be covered include boundary scan and functional test integration strategies; advancements in vectorless test techniques; incorporation of limited access electrical test techniques; test strategy analysis tools; high accuracy pin drivers and sensors; concurrent test throughput improvement options; scalable test performance capability architecture; and program development accelerators.
The paper describes how these new ICT advancements contribute to lowering overall manufacturing test costs by improving the fault coverage,reliability,and throughput of in-circuit production tests.

Although the vast majority of electronic equipment has made the transition to lead-free without significant issue,some market segments still utilize tin-lead solder. The European Union’s RoHS legislation currently exempts server,storage array systems and network infrastructure equipment from the requirement to use lead-free solder (exemption 7b). The reliability of network infrastructure equipment in Finance,Health Care and National Security applications is critical to the health and safety of consumers,countries and the global community and the long term reliability of these end products using lead-free solder is not completely understood.
In addition to Government regulations,the conversion of high end server and network applications to lead free is also being hastened by the limited availability of tin-lead components. Although the exact conversion date is unclear,the requirement to ultimately convert these complex products to lead-free is absolutely clear.
The successful transition of low end and mid-range server applications to lead-free has come largely through wave solder process optimization and the use of alternate lead-free alloys for mini-pot rework.
Copper dissolution has become an industry buzzword and numerous studies have concluded that the current industry standard procedure of using the mini-pot for PTH Rework will not provide the capability to rework extremely large,high thermal mass network/server PCB’s even when SAC305 is replaced with alternate lead-free alloys such as SN0.7Cu0.05Ni (SN100C) with lower copper dissolution properties. These new rework challenges are reviewed in detail along with potential alternatives to mini-pot rework for these high end applications.

Automated Optical Rework (AOR) is a new method of reworking shorts by using a fully automated fine laser beam to ablate
any excess copper in fine-line PCB patterns. This includes shorts,protrusions,copper splashes,minimum space violations,under etched conductors,excess features and more,without damaging the panel’s substrate.
In the traditional PCB production process,following automated optical inspection of a panel,the operator of the verification system manually reworks any excess copper using a knife. Manual rework can damage the adjacent conductor,penetrate the
laminate,create cosmetic defects in outer layers and more. In fine-line production (sub 60µm),quality manual rework is not
possible,even by highly skilled operators. This includes,for example,the most advanced smart phone designs with line and space of sub 50µm and prepreg lamination thickness of 40µm and below. In addition,many PCB shops’ customers prohibit manual rework of PCBs. The technological solution for automated rework that has been developed offers: • Support for fine-line products (down to L/S resolution of 30µm).
• Fast rework - typically 60 reworks per hour (including handling) for typical high-end HDI production
• High quality – minimum damage to laminate; typical penetration of 15µm or less
• Accuracy - deviation from reference of less than 10% • Repeatability - all reworks are of the same high quality • An automated process – no human intervention AOR introduces a closed-loop technology of iterative processes that consist of three parts: • Image acquisition - captures white-light and UV images. • Image processing - analyzes and compares the images with the CAM reference data and defines the accurate ablation contour and parameters. • Laser ablation - based on the processed data,shorts are reworked using laser ablation The quality results of AOR are now well-proven for even the most complex PCB designs. The latest technology
breakthrough in higher speed with no compromise on rework integrity has cleared the way for more widespread and mainstream use of this technology in the manufacture of today’s demanding PCB applications. The advantages of AOR provide new opportunities for fabricators to move much closer to achieving zero scrap production,while continuing to push the boundaries of electronics innovation. This technical paper will describe Automated Optical Rework technology and its advantages for advanced printed circuit
board production including examples of actual before and after results.

As more components are becoming lead free and not available in the tin lead alloy,there is an industry wide interest when it comes to the reballing and the subsequent effects it has on the strength of those components. This is particularly true for legacy parts needed for military applications some of which use tin lead solder. There is cause for concern due to the potential mixing of alloys and the differences in reflow temperatures of the two different alloys. Additionally,there are unknown characteristics regarding the intermetallics that are formed due to the potential of mixed alloys. This research paper will focus on the effect of various parameters that are used to reball a BGA and their effect on the overall shear strength. Factors that will be looked at include the type of BGA (SAC305 or 63Sn/37Pb),the alloy used to reball (SAC405 or 63Sn/37Pb),the type of flux used (Water Soluble or No Clean),and the environment in which reballing takes place (Nitrogen or Ambient). Being most relevant to industry demands,the focus will be on the effects of reworking a BGA with a base alloy of SAC305 and reballing it with 63Sn/37Pb. After the reballing of the component is complete,samples will be both shear tested and cross sectioned as a method of evaluation. The shear tests will determine the strength of the newly formed solder balls while the cross sections allow for the observation of the solder ball and the bonding characteristics of the new solder alloy to the pad on the BGA. The cross sections will also allow for observation of any defects or abnormalities through the reballing process. When the experimentation is completed,the goal is to determine the optimal factors that should be used in the creation of a robust process for BGA reballing.

•Jet printing introduction
•Industry challenges
•Jet printing low temperature paste
–Collaboration Alpha-MYDATA
–Rheology
–Results
•Low temperature paste offers a production solution for advanced applications
•Jet printing furthers these opportunities

Low Temperature Conversion
•Substantial cost savings over regular processes
•Savings can outweigh paste cost differences
•Can be mechanically stronger if done right
•Involves more than just changing pastes
•Beware of excessive flux residue
•Pick on plastic components / flex circuits
•Avoid high peak temperature

Low temp solders are a viable solution and their
performance can be enhance thought final finish
selection.
Initial data suggest that an organic metal final finish
in combination with a low temperature solderpaste
can out perform standard paste and OSP in the tests
performed.