BGA Rework is now largely mature,although new supplemental processes that provide improved process control such as
Solder Paste Dipping and Non-Contact Site Cleaning can now be integrated into existing processes if the rework technology that is used allows. So what are the next set of challenges that will need to be addressed in regard to Area Array and SMT Rework? The
International Electronics Manufacturing Initiative or iNEMI has recently published its 2013 Technology Roadmap for the
global electronics industry which includes a section dedicated specifically to rework and repair. Of particular interest and importance is iNEMI’s gap analysis which identifies future specific gaps and challenges that will result from such factors as
government regulations,disruptive technologies and new product requirements. This paper will review five of the key rework gaps and challenges identified by iNEMI including: 1) Reworking very large,next generation area arrays on large high thermal mass assemblies. 2) Development of hand soldering processes for reworking 01005 components. 3) Development of industry-standardized processes for reworking Package-on-Package (PoP) devices. 4) Development of industry-standardized processes for reworking Quad Flat,No Lead (QFN) devices. 5) Development of site redressing processes that prevent lifted pads,solder mask damage and copper dissolution
The objective of this paper is to discuss the five iNEMI rework gaps and challenges including identification of the key technical/process challenges,outlining in detail the efforts-to-date aimed at addressing these new challenges as well as the
next steps required for complete resolution of these challenges.

Commercial-off-the-shelf column grid array packaging (COTS CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This paper presents rework and re-column attachment of two high input/output (I/O) CCGA (CGA) packages (560 and 1144 I/Os). Subsequent to re-column attachment and isothermal aging,the integrity of tin-lead solder-column attachment was determined and presented. In addition,the process-control parameters for assembly of re-columned CGA packages using either vapor-phase or rework stations were established for both package types/sizes. Details of these process control parameters solder paste-print uniformity as well as quality assurance indicators based on visual inspection before and during thermal cycling tests are presented. Qualification guidelines generated based on these and additional optical photomicrographs,X-rays,SEMs,and destructive cross-sectioning of thermally cycled,reworked,re-columned,and re-assembled test vehicles of these CGAs are presented in detail.

Assembly defects can effectively shorten reliability lifetimes in addition to lowering manufacturing yields or creating premature service failures. This paper describes and characterizes an unusual open circuit failure mechanism in Pb-free ball grid array (BGA) solder joints. The failure occurred during Pb-free solder assembly of a 31 mm,1.27 mm pitch,perimeter array,SAC305 (Sn3.0Ag0.5Cu) BGA. Due to design constraints,it was necessary to assemble some BGA components during the first reflow cycle. Following the second reflow operation,some solder joint opens were detected on the BGA component which had been subjected to the atypical second reflow exposure. Metallographic cross sectional analysis indicated that the open solder joints initially were well-formed but the failure resulted from a brittle interfacial fracture at the package side of the solder joints. The failure mechanism and possible root cause is discussed in terms of the combined impact of stress induced by component and board warpage and the lower inherent strength of the solder joint near the melting and solidification temperatures.

In the past few years,several papers,test methods and methodologies have been developed to estimate pad cratering under Ball Grid Array (BGA) pads in Printed Circuit Board Assemblies (PCBAs).
However,almost all the tests and methodologies proposed so far have the following shortcomings:
1. They are destructive. The samples tested are broken and the failure mode(s) observed to determine the propensity for
cratering
2. They require testing several samples using different test methods (bend,shock,pull,shear or acoustic),but there is no easy correlation between the different test methods.
3. They can be used for relative comparisons,but there is no easy way to translate the correlations into failures in actual functional board level assemblies.
While these tests have helped mitigate pad cratering significantly,the industry still needs the following:
1. A non-destructive way to predict whether a certain PCBA design (BGA and PCB combination) is likely to result in mechanical strain induced pad cratering failures,long before the product has been built.
2. An easy to use way to correlate PCB level pad pull tests done per IPC-9708 and monotonic bend tests per IPC-9702,so that the design can be optimized to mitigate pad cratering failures during qualification testing.
3. An easy to implement design to detect pad cratering in a functional assembly,so that if a failure is observed in the field,it is easy to determine if the failure is due to pad cratering. Detecting a failure as soon as it occurs is critical in identifying the source of the mechanical strain that resulted in the failure,which in turn can help
quickly resolve the issue.
In this study,using extensive experimental data,a detailed methodology is outlined to show the relationship between board
strain,solder joint strain and force to failure in monotonic bend testing and pad pull testing. In addition,the correlation between monotonic bend testing and pad pull testing is shown,such that the results of pad pull testing can be used to estimate the likelihood of observing pad cratering failures in PCBAs during bend testing and manufacturing operations. The methodology can be used by designers to estimate the optimal combination of package and PCB design variables to minimize the likelihood of pad cratering and other solder joint failures during testing and field operation.
Finally,methodologies to predict and determine pad cratering failures quickly in field operations are also discussed and
outlined.

Test

Executive Summary
There are many issues to consider when developing a new circuit material for the PCB industry. It is a given assumption that the new material must be compatible to standard PCB fabrication processes and that by itself is a daunting task. The desired properties of new materials today are also to be robust in multiple lamination cycles,repeated lead free solder reflow cycles,multilayer capable and have consistent electrical performance.
This paper outlines a new material which meets the needs mentioned and is also halogen free,very robust to thermal cycling and is a consistent mid loss material.
Theta® circuit materials (TH) is a new material and in this study it was compared to many other materials in the industry. Since there was no known material with the same properties,a direct comparison was not available. Comparison to industry known good materials for different properties were used for this study.
Another test of thermal process stability is the eyebrow crack test. This is done on a multilayer with several layers of stacked via’s. When exposing the circuit to 288°C solder float,a circuit with good thermally robust material will typically withstand 3X cycles and the TH materials were good after 6X cycles. The pictures below shows the circuit made with the TH materials on the left,after passing 6X soldering cycles and another circuit to the right with different materials which failed after 3X cycles.
The electrical performance is also important and especially for high speed digital applications. In those applications dispersion can be important. Dispersion is how much the dielectric constant of the material will change with a change in frequency. The following graph shows dispersion curves of three materials.

With the miniaturization of components in the semiconductor industry,the need for specialized solder pastes with finer powder mesh sizes for package-on-package (PoP) assemblies has become imperative and increasingly more common. As the powder mesh size decreases (smaller diameter powder),more surface area of powder within the paste is exposed and,therefore,more susceptible to oxidation. The flux vehicle of the solder paste consequentially has more oxides to remove in order to allow for proper coalescence to form a good solder joint. The intent of this paper is to evaluate whether the decreased powder mesh size and increased oxide content of the powder in the PoP pastes affects the voiding performance of the materials,and to what degree.

Lead-free solder is more than a swap for SnPb and more than simply an alternative alloy. Five years after implementation discussion remains regarding which alloy is the best for which application. Alternative lead-free solders are available with doping of small amounts of elements to improve reliability. This study is compares Sn3,0Ag0,5Cu with low-silver Sn1,0Ag0,7Cu0,05NiGe and Sn0,7Cu0,05NiGe,a modified SnCu alloy.
A design of experiment was done to define the process window of the different alloys. Different flux preheat and solder temperatures were part of the experiment. For each alloy,the preferred parameters were defined to establish a reliable soldering process. The boards were soldered using these settings and reliability levels were tested. The test boards included different pad and barrel dimensions. This returns recommendations for designers to define the optimal pin-to-hole ratio for the different alloys.
For each alloy,the test boards were thermal cycled at -40C/+125C (30’/10”/30’) and aged at +125C for 1000 hours. The study included tensile strength measurements,intermetallic thickness growth,cross sections and visual inspection according to IPC standards.
The same alloys were used for reflow soldering. Solder paste with the same flux chemistry was used to perform reliability experiments. The presentation discusses the alloys’ performance. It also explains the benefits of adding small elements to an alloy and how to establish a compatible selection for reflow and wave alloys.

Electronic Assemblies are cleaned in order to remove contaminations that may affect yields,service life and reliability. Highly dense interconnects entrap flux residues under the Z-axis. Volatile solvents commonly used for cleaning include trichloroethylene,normal propyl bromide and a variety of other blended compounds (HFE,HFC,HCFC,etc.). Some of these solvent can have negative effects on the environment and workers. Alternative volatile solvents suitable for cleaning highly dense interconnects are needed. The purpose of this research to introduce an innovative method for cleaning electronic assemblies using a low volatile cleaning fluid followed by rinsing in an environmentally safe volatile solvent. Dual solvent cleaning provides a means for engineering cleaning fluids that match up to the soil and to be rinsed using a volatile solvent blend. This research will also report process integration between the cleaning fluids,cleaning equipment,and solvent recovery.

There are a variety of stencil approaches in which the new product process engineer can deal with the assembly of both high solder paste and low solder paste volume in an SMT assembly environment. Traditional approaches have heretofore favored aperture manipulation,multiple stencil printing and chemically or mechanically altered stencils which include a “step”. Some of these approaches present either a compromise or a non-workable option for building new products reliably and quickly. This paper presents a new approach delivering on the need for fast delivery and enough solder paste volume differential between the low solder paste and higher solder paste volume requirements. Presented will be the method and the results of an initial printing study determining amongst other things the solder paste volume delivered to the areas of different stencil height.