In the fast developing electronic industry the demands for production equipment are changing rapidly as well. The industry is looking for both,stable production processes and automated procedures in order to have full control of quality and costs.
This also affects the rework processes that are commonly still related to knowledge and skills of operators who are handling repair and touch-up of electronic assemblies.
To enable a rework system to carry out automated user independent rework the placement process needs to operate automatically. A new placement technology is introduced here that uses two cameras to identify the target area for component installation as well as the component pin structure. Image processing software calculates the correct placement position for the component out of the image information. A motorized four axes system is able to move the component to the target position without interaction of any operator. The procedure is based on an automatic pin detection algorithm along with a matching algorithm to find the correct position of the pin pattern in the target image. Several alignment procedures as well as camera corrections are implemented in order to reach the high demands of placement accuracy and repeatability.
The new placement technology relieves the user from exertive optical alignment and time consuming manual adjustment as well as guaranteeing a high repeatability in the positioning results. While the system is placing and installing the component the user can focus on preparative activities.
Besides automatic placement,the described rework technology allows automatic component flux and paste dipping as well as handling of paste printed components. Additionally soldering and desoldering processes are operated automatically.

As the Electronic Manufacturing Services (EMS) industry makes a push to bring manufacturing back to the United States it is clear that automation is necessary in order to keep prices competitive. The problem with automation in the EMS industry is the constant changing of designs and short life cycles of products. With hard automation the return on the investment (ROI) on many lines is not possible and therefore the manufacturing is kept offshore with manual processes. There is a solution to this problem which will change not only how automation and manufacturing is done in the United States but around the world as well. By using generic automation that can be used for the manufacturing of many products with little change over time and a small reinvestment it will completely change the decision to automate a line.
The vision for the future back end assembly manufacturing facility is similar to the current SMT assembly line. There will be different modules and stations that can be put together and programmed to do all the processes required by the particular assembly. Then with a simple rearrangement,program adjustment and incorporation of raw materials the line will be ready to perform a new assembly. This will allow manufacturing companies to bring products to market faster,an improved yield and with less of an initial investment. This paper will go into detail of an example of this type of line being deployed in Flextronics.

With the electronic industry moving towards lead-free assembly,traditional SnPb-compatible laminates need to be replaced with lead-free compatible laminates that can withstand the higher reflow temperature required by lead-free solders. Lead-free compatible laminates with improved heat resistance have been developed to meet this challenge but they are typically more brittle than SnPb laminates causing some to be more susceptible to pad cratering. In this paper,two novel approaches for minimizing pad cratering will be discussed. Preliminary results which validate the two approaches will also be presented.

Pad cratering test methods have been under development with the emergence of this laminate fracture defect mechanism. In additional to ball shear,ball pull,and pin pull testing methods,the acoustic emission method is being developed to evaluate
laminate materials’ resistance to pad cratering. Though the acoustic emission (AE) method has been proven to be able to detect pad cratering,no study has reported which AE parameters are good indicators for the susceptibility of PCB laminates to pad cratering. In this study,six different laminates subjected to three different pre-conditioning (multiple reflow) cycles have undergone the four-point bend testing. Four AE sensors were used to monitor pad cratering during the bend test. Several AE parameters including amplitude in dB level,the energy,and the location of each AE event under different load levels are recorded. Location analysis shows the majority of AE events are concentrated in the largest BGA package in the
test vehicle,which indicates that pad cratering is elevated with the larger size of BGA package due to high stress concentration. Both the number of AE events and the cumulative energy of AE events at a given applied load show that Laminate F is prone to pad cratering. However,there is no statistically significant difference in the lowest applied load to detectable AE among these six laminates. The ranking of the six laminate materials is different using different test methods. The most effective test method for predicting pad cratering susceptibility is inconclusive from this study.

Pad cratering is an important failure mode besides crack of solder joint as it’ll pass the regular test but have impact on the long term reliability of the product. A new pin pull test method with solder ball attached and positioning the test board at an angle of 30º is employed to study the strength of pad cratering. This new method clearly reveals the failure mechanism. And a proper way to interpret the finite element analysis (FEA) result is discussed. Impact of pad dimension,width and angle of copper trace on the strength is included. Some findings not included in previous research could help to guide the design for better performance.

Stencil nanocoatings have demonstrated significant improvements in numerous aspects of solder paste printing,including print yield,transfer efficiency,print definition and under wipe requirements. By lowering the surface energy of SMT stencils,they reduce flux bleed out around the perimeters of apertures and enable cleaner paste release during stencil-PCB separation.
With several years of commercial success behind the original nanocoating materials,a new generation has been developed that improves upon many of the characteristics of the original formulations. Advancements in durability,detectability and cost boost the overall performance of these flux-repellent stencil treatments. Numerous tests have been performed to characterize stencil nanocoating materials throughout their development cycles and quantify their actual performance in SMT production environments. Laboratory tests have used liquid contact angles as response variables to characterize chemical and abrasion resistance and overall repellency. Production environment print tests have used automated solder paste inspection (SPI) to quantify volume repeatability,transfer efficiency,wipe frequency and overall print yields. These studies have focused on the end results of coating durability and print quality improvements,but have not explored the relationship between flux flow and surface energy modifications on the underside of the stencil. The novel test approach reported in this paper used solder paste treated with UV tracer dye to help image the flow of the flux on the bottom of the stencil (fig 1). This paper reviews the test methods and results,and describes the chemical structure of Self Assembling Monolayer Phosphonate (SAMP) nanocoating materials and their influence on the solder paste printing process. The discussion concludes with an overview of related applications of SAMP treatments in the SMT assembly,including printer tooling and accessories,area array/BTC rework stencils and jigs,and placement nozzles.

The goal of this study was to develop a method by which stencil aperture wall quality can be inspected,and the results quantified. Additionally,we hope to establish a correlation between the stencil wall quality and the paste release performance.
Stencil quality studies have traditionally focused on release data as the main method of gauging stencil fabrication quality. While some studies have included SEM images to aid in the assessment of stencil aperture wall quality,none have provided a method for quantifying the stencil wall smoothness. In this study,we will measure aperture walls of stencils using a confocal white light sensor with a 3 micron spot size and 0.02 micron depth resolution. The results will be quantified as average surface roughness (Sa). The surface roughness of various stencil fabrication methods will be measured and compared. Vendor claims of the quality of various materials,such as 304 Stainless,more expensive premium foils and nickel,will be assessed as will different fabrication methods including laser cutting,e-form and nano coating. In order to understand how wall roughness impacts stencil performance,a paste release study will also be conducted. A single BGA pattern will be printed on a glass slide and the paste release will be measured. This study will be of interest to both fabricators and users of stencils.

There has been recent activity and interest in Laser-Cut Electroform blank foils as an alternative to normal Electroform stencils. The present study will investigate and compare the print performance in terms of % paste transfer as well the dispersion in paste transfer volume for a variety of Electroform and Laser-Cut stencils with and without post processing treatments. Side wall quality will also be investigated in detail. A Jabil solder paste qualification test board will be used as the PCB test vehicle. This board has a wide range of pads ranging from 75 micron (3 mil) squares and circles up to 300 micron (12 mil) squares and circles. There are also long rectangular pads with spacing’s as low as 75 micron (3 mil). A total of 12 stencils,four stencils of different stencil technologies with three different coating configurations,will be tested as described in 1-4 below:
1- Electroform w/o Nano Coat and with and Nano Coat A and Nano Coat B
2- Laser-Cut Electroform foil w/o Nano-Coat and with Nano Coat A and Nano Coat B
3- Laser-Cut Fine Grain SS w/o Nano Coat and with Nano Coat A and Nano Coat B
4- Laser-Cut Fine Grain SS with Electropolish and Nickel plating,w/o Nano Coat and with Nano Coat A and Nano Coat B
A 100 micron (4 mil) thick stencil is used for all 12 stencils yielding Area Ratios ranging from .31 to .1.21.

With increasing power loss of electrical components,thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Due to the rapid advances in semiconductor technology,particularly in the regime of high-power components,the temperature dependence of the long-term reliability is a critical parameter and has to be considered with highest possible care during the design phase.
Two main drivers in the electronics industry are miniaturization and reliability. Whereas there is a continuous improvement concerning miniaturization of conductor tracks (lines / spaces have been reduced continuously over the past years),miniaturization of the circuit carrier itself,however,has mostly been limited to decreased layer-counts and base material thicknesses. This can lead to significant component temperature and therewith to accelerated system degradation.
Enhancement of the system reliability is directly connected to an efficient thermal management on the PCB-level. There are several approaches,which can be used to address this issue: Optimization of the board-design,use of base materials with advanced thermal performance and use of innovative buildup concepts.
The aim of this paper is to give a short overview about standard thermal solutions like thick copper,thermal vias,plugged vias or metal core based PCBs. Furthermore,attention will be turned on the development of copper filled thermal vias in thin board constructions. In another approach advanced thermal management solutions will be presented on the board level,exploring different buildup concepts (e.g. cavities). Advantages of cavity solutions in the board will be shown,which not only decrease the thermal path leading from the high power component through the board to the heat sink,but also have an impact concerning the mechanical miniaturization of the entire system (reduction of z-axis). Such buildups serve as packaging solution and show an increase in mechanical and thermal reliability.
Moreover,thermal simulations will be conducted and presented in this paper in order to reduce production efforts and to offer optimized designs and board buildups.

The ever expanding growth in the use of insulated metal substrates (IMS) in power electronics requires a focus on material and mechanical configuration for each application. By optimizing the material makeup and printed board format,performance and reliability expectations can be further achieved. The thermal performance and electrical isolation needs are driven by the power requirements,but considerations of temperature range,mechanical durability and format,along with the physical package surrounding the substrate must also be managed. With a variety of material configurations and circuit format capabilities,the choices become a balancing of options to maximize performance and minimizing cost through Design For Manufacturability (DFM) in the circuit board fabrication. These challenges present the IMS printed board fabricator with material selections and fabrication processes unlike those for other printed board or ceramic applications.