The choice and optimisation of underfills to maximise process productivity and end product performance has been widely studied,and generated numerous performance criteria,flow time cure schedule,CTE,and Tg to name but a few. The same can not be said of the rework process. By separating the rework process into a series of independent steps and setting performance criteria on each step it is possible to generate a rating system to compare both the performance of the underfill and the impact of changing the process setup. The weighting of the various steps in the final calculation can be adjusted to suit an individual application’s requirements to help optimise both the product and process for rework.

Smart phones are complex,costly devices and therefore need to be reworked correctly the first time.
In order to meet the ever-growing demand for performance,the complexity of mobile devices has increased immensely,with more than a 70% greater number of packages now found inside of them than just a few years ago. For instance,1080P HD camera and video capabilities are now available on most high end smart phones or tablet computers,making their production more elaborate and expensive.
The printed circuit boards for these devices are no longer considered disposable goods,and their bill of materials start from $150.00,with higher end smart phones going up to $238.00,and tablets well over $300.00.
The implementation of the surface mount devices have become key components for mobile products by offering increased component density and improved performance. For example,the newer style DDR memory integrated components use less power and work at twice the speed of former versions. It is not surprising that most component manufacturers now produce these surface mount devices as small as 1mm square.
Mobile products generally use an epoxy underfill to adhere components to the printed circuit board in order to meet the mechanical strength requirements of a drop test. Reworking glued components is the most difficult application in the electronics industry,and needs to be addressed as a process.

The company is a producer of thin film batteries of less than 0.45mm in thickness. Battery operated devices have grown
smaller and smaller while energy demands have increased as the need for increased functionality has grown. This need has
led designers,which would normally use conventionally sized batteries,to consider other types and form factors. Products
such as powered display transaction cards,RFID/sensor tags,and medical device patches have created a market for thin film
batteries.
The following provides a brief review of battery construction. All batteries are basically made up of an anode (lithium in this
case) and a cathode (MnO2 in this case),separated by a mechanical barrier (separator layer) designed to prevent internal
electrical connectivity. The trick with the separator layer is to minimize resistance within the battery by being thin while not
too thin as to promote soft shorts,limiting the life of the battery.

Polyester film substrates have been widely used in making flexible / printed electronic devices for over 30 years. However the early 2000’s brought about an explosion of interest in “additive” printed electronics in terms of developing materials and device technology while exploring new business opportunities. This next generation of Flexible Electronics technologies has required materials suppliers to deliver improved functionalities to the device developers in fields as wide as electrophoretic displays,backplanes,barrier films,sensors etc... Over this period,substrate suppliers have worked closely with the flexible electronics community to understand and define the evolving film requirements of this embryonic industry. This presentation will initially give an overview of substrate evolution for flexible electronics,exploring the typical issues associated with substrate development and selection. The talk will then lead on to discuss the latest film developments in support of the flexible electronics industry,including dimensional stability,environmental protection,surface quality,refractive index matching,and optical clarity.

Using micro-dispensing with exceptional volume control it is possible to print in 3D space a wide variety of materials and including solders,epoxies,conductive adhesives and ceramic filled polymers. These can be used to build 3D structures and utilizing a 3D Printing approach which is also known as Computer Aided Design and Computer Aided Manufacturing (CAD/CAM). The advanced technology enables 3D printing of electronics but it also enables smaller solder and adhesive dots; 75 microns and less. It is possible to place these on any package in 3D space. Demonstrations for this technology have shown that it is possible to print less than 50 micron wide lines and dots. Additionally a wide range of materials that will be required in future packaging can be dispensed. These smaller features provide sub nanoliter volume. This is possible given the less than 100 picoliter volume control during dispensing and including highly viscous materials. Demonstrations of smaller printed dots and lines for electronic circuits and packaging will be shown. In addition,3D circuitry that is 3D printed and contains no solder will also be shown,demonstrating the future of printed circuits.

Product quality can be improved through proper application of design for test (DFT) strategies. With today’s shrinking product sizes and increasing functionality,it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques,such as boundary scan,help to recover this loss of test coverage. However,many of these test techniques need to be designed into the product to be effective. This paper will discuss how to maximize the benefits of boundary scan test,including specific examples of how designers should select the right component,connect multiple boundary scan components in chains,add test access to the boundary scan TAP ports,etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally,this paper will include a description of some advanced test methods used in in-circuit tests,such as vectorless test and special probing methods,which are implemented to improve test coverage on printed circuit boards with limited test access.

This iNEMI program's focus is on a “Chip” Built-in Self-Test (BIST) study and its promotion for board and system-level applications. In this case,This study has 2 strategic focus areas – short term that involves “what chips already have”; and long term that involves “defining specific chip content to meet board test goals.” Presently,there are there are too many algorithms and too many interfaces – some standard and some custom – there is no agreement across the industry as to a “single” standard. In addition,the algorithms are usually standard and are for IC Test which are overkill for board test. In fact,the term BIST is overloaded in that it can be used by IC providers in association with Logic,Memory,SerDes,PLL’s and other functions. Most “chip” level BISTs are designed to aid IC manufacturing; these tests and algorithms are often not suitable or available to run at the board level – but if thay can be operated by board test,they can usually be used to meet some board test needs. The goal of this iNEMI program is to:
• Develop and promote the adoption of IC BIST to meet test and debug needs at the board/system level,
• Encourage IC vendors to provide standard chip BIST access interfaces and algorithms for board test and debug
• Encourage ATE/Instrument providers to develop products based on existing related standards for BIST design.

For example,an IEEE 1500/P1687 globalized Test Cost Model useful throughout the industry. The iNEMI BIST Program consists of four phases: 1. Survey on BIST availability,usage,access at board level test (Phase 1 - complete). 2. Component BIST Use Case Investigation Project (Phase 2 - complete). 3. Component BIST Short-Term and Long-Term Strategies for Use Case Classification Project (Phase 3 – in progress). 4. Board Level Test Recommendations for Standardization of Component BIST (Phase 4). The work presented here by the iNEMI Built-In Self-Test (BIST) Project,Phase 3 Short-Term and Long-Term Strategies for Use Case Standardization,takes a more comprehensive view of the problem. The thrust of the work investigates and identifies a function classification of the “Use Case” as defined in the BIST “Use Case” Investigation Project (Phase 2 – “What are my board Test Problems that a BIST could Assist”),where the proposed Use Case incorporates an ASIC/CPU/FPGA to memory interface. The classification includes the following tasks: Listing of tests and tasks performed; logic/features involved in the tasks and tests; access,control,and configuration requirements; test,function,and feature access to set up and run tests.

The number one issue identified by the 2009 iNEMI Boundary-Scan survey was problems with obtaining correct and compliant boundary-scan description language (.bsdl) files from the semiconductor industry for use in boundary-scan printed circuit board assembly (PCBA) test generation. The major conclusions from the survey were:
• The semiconductor industry needs to make a greater effort to produce correct and compliant BSDLs.
• A better job needs to be done verifying JTAG hardware compliance to .bsdl files.

Non-compliance is typically found when a test is generated and it doesn’t work! The consequences of not having correct and compliant .bsdl file to generate boundary-scan tests is the inability to generate boundary-scan and if tests cannot be generated,the result is lower overall test coverage for PCBAs,resulting in higher manufacturing costs and lower overall product quality. The work presented here by the iNEMI Boundary Scan Phase 3: Investigation into Challenges of Using .BSDL Files Project group takes a more comprehensive view of the problem by surveying the industry to determine if issues associated with IEEE 1149.1 .bsdl files identified in the 2009 iNEMI Boundary-Scan survey still exist,and if so to what extent,and identify any new issues. Based on the data obtained,the results will be used to raise industry awareness of the issues and potential solutions. Current and best practices for .bsdl file creation and validation will be identified and documented.

The number one issue identified by the 2009 iNEMI Boundary-Scan survey was problems with obtaining correct and compliant boundary-scan description language (.bsdl) files from the semiconductor industry for use in boundary-scan printed circuit board assembly (PCBA) test generation. The major conclusions from the survey were:
• The semiconductor industry needs to make a greater effort to produce correct and compliant BSDLs.
• A better job needs to be done verifying JTAG hardware compliance to .bsdl files.

Non-compliance is typically found when a test is generated and it doesn’t work! The consequences of not having correct and compliant .bsdl file to generate boundary-scan tests is the inability to generate boundary-scan and if tests cannot be generated,the result is lower overall test coverage for PCBAs,resulting in higher manufacturing costs and lower overall product quality. The work presented here by the iNEMI Boundary Scan Phase 3: Investigation into Challenges of Using .BSDL Files Project group takes a more comprehensive view of the problem by surveying the industry to determine if issues associated with IEEE 1149.1 .bsdl files identified in the 2009 iNEMI Boundary-Scan survey still exist,and if so to what extent,and identify any new issues. Based on the data obtained,the results will be used to raise industry awareness of the issues and potential solutions. Current and best practices for .bsdl file creation and validation will be identified and documented.

Increasing system integration and component densities continue to significantly reduce the opportunity to access nets using standard test points. Over time the size of test points has been drastically reduced (as small as 0.5 mm in diameter) but current product design parameters have created space and access limitations that remove even the option for these test points. Many high speed signal lines have now been restricted to inner layers only. Where surface traces are still available for access,bead probe technology is an option that reduces test point space requirements as well as their effects on high speed nets and distributes mechanical loading away from BGA footprints enabling test access and reducing the risk of mechanical defects associated with the concentration of ICT spring forces under BGA devices.
Building on Celestica's previous work characterizing contact resistance associated with Pr-free compatible surface finishes and process chemistry; this paper will describe experimentation to define a robust process window for the implementation of bead probe and similar bump technology that is compatible with standard Pb-free assembly processes. Test Vehicle assembly process,test methods and "Design of Experiments" will be described. Bead Probe formation and deformation under use will also be presented along with selected results.