Electronic Board Defect Classification and Detection with Deep Learning

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Inspection means have increasingly been incorporated into typical manufacturing of boards, substrates and/or systems. A significant number of automatic inspections rely on the analysis of images that are acquired by a multitude of means such as Optical, X-Ray, Infrared, Acoustic microscopy. In contrast to automatic inspections, traditional visual inspection is performed manually by humans based on images and can be laborious and inaccurate. Detection of “indeterministic” defect types such as cracks and/or scratches is quite challenging since such defects may have a variety of shapes, locations and severity. Deep Learning, a subfield of Machine Learning, has recently advanced the state-of-the-art learning from images and become the standard approach for computer vision tasks. This paper presents a case study for automating visual inspection of boards by as much as 40%. The application can be extended to identify specific types of defects and to support root cause analysis.

Author(s)
Dan Sebban and Nissim Matatov
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Beyond The Hype -The Digital Twin Demystified

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Digitalization changes everything, everywhere. It is inevitable, new business drivers are forcing the Electronics industry to rethink every element of their business. Virtually every company is talking about innovation and digitalization. And a major driver is the so-called Digital Twin. While talking about this Industry 4.0 enabler, most people have one benefit in mind: Aggregating the data in a cloud and integration of artificial intelligence for future enhancements which lead to an optimization of the operation. Another one is the simulation of a product and derive the behavior in certain conditions. Both are covering only one certain aspect of the product lifecycle from product design to production execution while there is so much more possible by utilizing the concept of the digital twin in the production engineering phase via Virtual

Commissioning. Streamline the activities of all disciplines involved in the physical commissioning of their automated production systems, reducing errors and increasing the speed in which they bring automated manufacturing systems online by writing the controller program and building the machine at the same time. The paper will review the different digital twin concepts in production:

-Digital Twin of the product: Product design, Hot Spot simulations and adoptions, simulate PCB circuit design-Digital Twin of production workflow: Machinery design, production layout, simulation of production steps & continuous improvement including manual labor-Digital Twin of manufacturing: The emphasis of the presentation will be within this discipline of the digital twin. Steps

1.Write PLC (Programmable Logic Control)/Controller code for machine operation

2.Define sensor and actuators (conveyors, robots, grippers,...) in the CAD model as input and output signals according to the PLC code

3.Define collision models and kinematics in the CAD model (e.g. a product falls over at the end of a conveyor belt or a robot arm must not collide with the chassis of the production cell)

4.Test your machine functionality in the digital twin.

Since physical behavioral model is defined within the CAD model the integration of the PLC code allows to detect failures in the construction of the machine (e.g. robot arm cannot reach a defined position in the process or conveyor belt cannot transport defined parts smoothly) which can be corrected prior to the actual construction of the machine. As a result, the generated PLC code is validated before the machine is even built and reduces the real commissioning time dramatically.

In the provided use case the example will show the collaboration between the end customer and a Chinese OEM, where the machine was constructed in China and PLC code written in Germany with the integration into the CAD model. After the shipment of the machine to Germany the validated PLC code was downloaded smoothly and no structural changes were necessary. Needed changes were recognized beforehand in the Digital Twin model of the machine and communicated to the OEM during construction phase in order to amend the machine design.

The last Digital Twin use case will be the Digital Twin of performance with closed-loop innovation by aggregating data in a cloud and run analytics for further improvement of future production machines or prescriptive maintenance mechanisms.

Author(s)
David Rogers
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Winners of IPC Hand Soldering Competition at Instrutec 2022 Announced

In conjunction with Instrutec 2022 and the Estonian Electronics Industries Association, IPC hosted its popular IPC Hand Soldering Competition in Tallinn, Estonia October 12-14, 2022, welcoming 31 competitors from 14 European electronics companies.    

Skilled contestants competed to build an assembly in accordance with IPC-A-610 – Class 3 criteria, and were judged on the functionality of the assembly, compliance with the assembly process, and overall product quality. Contestants were allowed a maximum of one hour to complete the process.

On the winner’s podium at Instrutec 2022 were:                                               

First Place: Returning first prize winner, Timmo Antso, Scanfil. He received a certificate, a cash prize of 300 EUR, a soldering station from sponsor Hakko, and a gift from sponsor Almit. As the winner, Ansto qualified for the IPC Hand Soldering World Championship at electronica in Munich, Germany, November 15–18, 2022. 

Second place: Ave Esko, Scanfil. She received a certificate, a cash prize of 200 EUR, and a soldering station from sponsor Hakko, and a gift from sponsor Almit.

Third Place: Karen Andresoo, Enics. She received a certificate, a cash prize of 100 EUR, a soldering station from sponsor Hakko, and a gift from sponsor Almit.

Best Company Team Award

IPC and the Estonian Electronics Industries Association presented the Best Company Team Award, recognizing the company which engaged the best team, with overall score based on the best scores of competitors from that company. All companies that registered two or more competitors were automatically entered into the Best Company Team category. For the Estonian competition, 11 companies were eligible for the Best Company Team Award. The top prize was presented to Scanfil, with a winning score achieved by Scanfil competitors Timmo Ansto and Ave Esko.

IPC thanks the Instrutec tradeshow and the Estonian Electronics Industries Association for hosting the event. IPC is grateful to the HSC sponsors for their generous support:

  • Gold sponsors: Hakko, Thales, and Ateliers System
  • Silver Sponsors: Optilia, Almit, Polygone CAO, SFM-Societe Française de Microscopie, the local IPC licensed training center Tallinna Polüteknikum and the Estonian Electronics Industries Association

“IPC thanks and congratulates all the participants and their companies for their interest and for taking up the challenge,” said Philippe Leonard, IPC Europe director. “We look forward to seeing all of the first-place winners compete in the Hand Soldering World Championship at electronica in Munich, next month.”

For more information on HSC competitions in Europe, contact Leonard at PhilippeLeonard@ipc.org.

Attendees can Meet, Greet, Connect and Expand their Network at IPC APEX EXPO 2023

IPC APEX EXPO 2023 attendees can meet with electronics industry innovators and connect with peers all in one place at the San Diego Convention Center, January 21–26, 2023.

From the exhibit floor to the classroom and everywhere in between, including the show floor welcome reception, poster presentations, newcomers networking reception, exhibitor product showcase corridor, ice cream social on the show floor, women in electronics networking reception; and more, attendees can meet, greet and connect at special networking events throughout IPC APEX EXPO 2023.

Among the highly anticipated special events is opening keynote by mechanical and aerospace engineer, host and co-producer of Emily’s Wonder Lab on Netflix, and executive producer and host of Xploration Outer Space on FOX, Emily Calandrelli. On Tuesday, January 24, Calandrelli will present, “The Sustainability, Economics and Advocacy of Space Exploration,” addressing how space exploration is helping life here on Earth and providing an overview of the innovation occurring today -- where we’re headed and the economics and advocacy behind it all.

New in 2023 will be a career connection event with special guests from IPC’s Emerging Engineer program who will lead a discussion on forging a career path by taking risks and looking for opportunities. Advance registration for the career connection networking event is required and is free with the All-Access Package; registration for this event is $40 if registering separately.

“Special events at IPC APEX EXPO provide tremendous value for attendees,” said Alicia Balonek, IPC senior director of trade shows and events. “And, when it comes to career development and advancement it’s not only what you know it’s also who you know. Thousands of industry leaders, manufacturing innovators and subject matter experts from across the globe will convene at IPC APEX EXPO 2023, making it the place to be to help you build company and personal networks and advance careers to the next level. This is what makes the IPC APEX EXPO experience priceless.”

The event essentials pass as well as access to the exhibit hall is free to those who register by January 21, a savings of $40 on-site. Attendees who register by December 16 will save 20 percent off registration fees. In addition, attendees who register for the All-Access Package will receive a significant percentage off a la carte options. Schedule and registration details are available at www.IPCAPEXEXPO.org.

Energy Efficient Reflow Soldering Process Using Embedded Carbon Layers

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As the reflow soldering process is the main energy consumer in a SMT assembly line, there is a high potential for cost reduction by significantly reducing the amount of energy needed. Melting the solder only needs a tiny percentage of heat, most of the energy is wasted to heat up the machine itself. If it would be possible to heat up only the solder joints to the required temperature the energy reduction will be substantial.

The crucial factor for such a process is to use a conductive heating material layer inside the printed circuit board (PCB) and generate the heat from inside by joule heating[2,3]. For this process it is necessary to have an electric current flow inside the heating material. This flow must be controlled as the heating layer is a carbon-based material and changes its resistance as a function of the temperature. The control circuit must be able to regulate the produced heat and generate a reflow like profile at the joints of every component on the PCB. The structure of the heating layer must be flexible as a result of having the possibility to adjust the amount of heat in a specific area of the PCB. So for a common PCB it will be necessary to have several connections from the current controller to the PCB.

In the joint research project “ERFEB” (Energy and Resource Efficient Production of Electronic Assemblies)[1], a current control unit will be designed and tested for different numbers of connections and different structures of heating layers to achieve a reliable reflow profile for a PCB soldering process.

Author(s)
Andreas Reinhardt, Arne Neiser
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Can 150μm Pitch Flip Chip be Done on Standard SMT Lines?

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As miniaturization trends continue in the electronics industry, System in Package (SiP) technology is gaining more and more traction. In many ways, some SiP modules are just surface mount technology in a high-density package. Component to component spacings are being driven even closer, pcb technology are migrating to package type substrates and more bare die are being used in these modules instead of conventional SMT (surface mount technology) packages.

This paper will discuss the flip chip process that has been developed for a 150μm pitch package, 10x10mm die size and greater than 3700 I/O full array solder flip chip. The test vehicle design will be shown, challenges that were faced during the process development, impact of warpage of the substrate on the flip chip yield and other factors that influence the successful assembly of these types of packages. This paper will describe processes from SMT and underfill and will touch on reliability test runs and the results of those testing.

Author(s)
David Geiger, Howard Osgood, Robert Pennings
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Investigating the Metric 0201 Assembly Process

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The advance in technology and its relentless develop mentis delivering yet another surface mount assembly challenge. To meet the market demand for products with higher functionality whilst reducing the overall product size, the next generation of chip package is being readied upon the surface mount community. The Metric 0201 will have dimensions in the order of 0.25mm x 0.125mm,as a result the entire assembly process will be questioned as to its ability to deliver high volume/quality product.

This paper will look at the challenges of assembling the M0201component in a high-volume manufacturing environment. The investigation will start with the printing process, with close attention to the impact of aperture and pad designs. The placement and reflow process will likewise be studied in detail.  The resultant assemblies will be reviewed to determine their suitability for a high-volume manufacturing environment. Discussion and conclusions will be directed at possible Metric 0201 assembly rules and the future challengers that exist.

Author(s)
Clive Ashmore
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Balancing Air Assisted Atomization for Improved Conformal Coating Quality

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Polymer coating materials protect electronics from harsh environments, assuring safe and reliable performance. To reach the highest level of reliability, coatings must be selectively applied to avoid keep out zones and critical components, such as connector pins, test points, and relays.

To gain better control over selectivity and eliminate the need for masking, manufacturers often choose to automate their conformal coating process. Air assisted atomization is commonly used in automated processes because it accommodates a wide range of material viscosities. The spray created when external air pressure is applied to the fluid stream provides excellent coverage on the sides of components and is cost effective. When atomization benefits are combined with properly characterized selective coating equipment, yield and throughput can also be increased.

Successfully atomizing the coating fluid relies on multiple factors including fluid chemistry and the amount of air assist applied. Fluid property requirements depend on the desired coating protection and are often defined before the coating equipment is selected.

An optimized spray pattern is determined by the results that appear on a coated board. And identifying the air assist settings to achieve that optimized spray pattern is an iterative process. Issues such as overspray, cobwebbing, and inconsistent pattern thickness can occur. When attempting to resolve these issues, air assist is typically increased or decreased. Unfortunately, these adjustments can introduce an imbalance that leads to amplified complications. If a manufacturer is unable to resolve issues quickly, they might choose to reintroduce manual activities –forgoing the cost savings, consistent quality, and other advantages that come with automation.

Author(s)
Camille Sybert Tim Girvin
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

CHIPS Act Implementation Requires Strong Focus on "Advanced Packaging," Industry Leaders Say

Ever-more complex packaging of chips will be the key driver of future innovation, yet the United States and Europe are behind the curve

Leaders of top semiconductor, microelectronic, IC-Substrate, PCB, EMS, and OSAT companies along with the U.S. government and European Commission gathered in Washington, D.C. last week to discuss "the next big thing" in CHIPS Act implementation: expanding "advanced packaging" capacities and capabilities to go along with expanding production of semiconductor chips.

The symposium and a new report, sponsored by IPC, were driven by the growing recognition that advanced packaging is increasingly the leading driver of innovation in microelectronics today. Advanced packaging capabilities in the U.S. and Europe remain weak, but both regions are now developing and funding strategies to develop this part of the semiconductor ecosystem.                    

The new report by IPC, based on a survey of nearly 100 industry leaders in semiconductors and related fields, shows strong industry support for increased public and private investments in advanced packaging efforts. For example, 94 percent of electronics industry leaders report that improving the performance of semiconductors is increasingly reliant on advanced packaging. And, 84 percent of electronics industry leaders believe government initiatives to bolster the semiconductor supply chain require significant investment in advanced packaging capabilities.

A previous IPC report found the U.S. has only just begun to invest in advanced packaging, while nations in Asia have the lion's share of capabilities and capacity.

The recently enacted U.S. CHIPS and Science Act authorizes at least $2.5 billion in Fiscal 2022 alone for a newly established National Advanced Packaging Manufacturing program. IPC is now part of a consortium led by the Semiconductor Research Corporation and funded by NIST to develop a federal road map for advanced packaging and related efforts. The Departments of Defense and Commerce and a new Industry Advisory Committee to the U.S. Government are also among those focusing on the issue.

The European Union has developed its own Chips Act which is currently before the European Parliament and European Council. IPC is working with industry leaders and partners to ensure that it, too, supports the growth of a robust advanced packaging ecosystem in the region.

“Advanced packaging is a key element in defining the next generation of semiconductor innovation. It is making possible spectacular new technology solutions to solve many of the world’s most pressing challenges. But in order to achieve these goals, companies and governments will need to determine how to cultivate robust regional advanced packaging ecosystems to support the expected surge in chip production globally,” said IPC Chief Technologist Matt Kelly.

Speakers at the symposium and the topics they covered included:

  • Packaging is the New King, Todd Younkin, Ph.D., President and CEO, Semiconductor Research Corporation (SRC)
  • Supporting Moore’s Law with Advanced Packaging, Tom Rucker, Ph.D., Vice President Technology and Development, Intel Corp.
  • Defense Perspectives Keynote: DoD Microelectronics Strategy, Devanand Shenoy, PhD, Director, Defense Microelectronics Cross-Functional Team, Office of the Under Secretary of Defense for Research and Engineering
  • NIST, Semiconductors, and the CHIPS & Science Act, Frank Gayle, ScD, Deputy Director, NIST Office of Advanced Manufacturing & Advanced Manufacturing National Program Office
  • Establishing Domestic Advanced Packaging Capability for DoD Applications, Helen Phillips, Director, Advanced Operations Northrop Grumman Mission Systems
  • Yesterday, Today, and Tomorrow on Package Substrate Industry, Richard (KwangWook) Bae, Executive Vice President of NPI, CTO, Samsung Electro-Mechanics Pte., Ltd. (SEMCO)
  • A Chips Act for Europe, Francisco J. Ibáñez, Senior Expert, Microelectronics and Photonics Industry, DG CONNECT, European Commission