Companies that have initiated internal resources to obtain compliance data have realized that collecting,and more importantly,maintaining the currency of that data requires more resources than available. For a case in point,one such company utilized 3 component engineers over 3 years to collect compliance data on ~5000 parts only to find out that all the data collected was now out of date. Why was it out of date? Among several reasons: the EU changed the method for reporting exemptions,REACH SVHC’s were added (several times) and manufacturers were forced to change and republish their declaration documents to meet these new requirements. Additionally,in North America Conflict Minerals declaration has been introduced demanding yet more documentation collection and maintenance. And,there will be more change.
Compounding the resource need is a lack of standardized data. All manufacturers publish in pdf,Excel,Word docs,etc,where there is no normalized standard. The data needs to be “lifted” from these documents and transferred to a parsed database. Quality and accuracy is at risk both from the supplier (~40% of supplier declaration documents are currently being returned to the manufacturer for correction) and the manual transfer process itself. Additional resources are needed in QA personnel with a specialized expertise in Environmental Compliance.
A centralized,publicly available database would be ideal if there were a method of ensuring quality of data served,however getting the industry to adopt a standard has not been possible. There are opt-in web services that require the manufacturer to normalize and upload data to a portal; however there is no quality control and no guarantee that all suppliers will participate leaving the need,once again for dedicated internal resources to provide specialized QA/CE collection and maintenance personnel.
A study was conducted to determine what internal resources would be needed to accurately collect,QA maintain and produce product level compliance reports on ~5000 components and material. Here is a list of the findings:
• 3-5 technicians to find and manually transfer the data from manufacturers published documents
• 2 component engineers to review and QA the physical characteristics of the data collected
• 2 Environmental compliance engineers to review,QA and manage the correction phase
• Database software
• IT implementation resources
Most companies do not have or can’t afford this reality. Since the manufacturers are not likely to adopt a standard method for publishing in the near term,and more change is inevitable,the only solution available today is a 3rd party data provider; one that does have the resources to collect,QA,maintain and deliver. Our study found that the fees for these 3rd party services are typically less than the cost to implement the necessary resources internally. Other IPC members can attest to this and their success.

The new plasma polymer PCB final finish that eliminates harsh chemicals and waste streams also promises to eliminate creep corrosion,but will it stand the test of time? Before any new product or process can be implemented,it must be tested extensively to demonstrate its fitness for use. Performance from the beginning to end of the product life cycle must be measured or simulated. For the new PCB finish,the gamut of testing included characterizing the application process,storage robustness,corrosion resistance,solderability and joint reliability. Methods used to test the coating included FTIR,EDX,mixed flowing gas,steam aging,wetting balance,thermal aging,shear testing,and micro sectioning with both SEM and optical microscopy. Over a year’s worth of testing performed by two independent US laboratories is presented in this paper. It details the purpose,method and results of each test and discusses the findings with respect to long-term performance.

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs,ADCs,and memory. They are susceptible to electrical,mechanical and thermal modes of failure like other components on a printed circuit board,but due to their materials,complexity and roles within a circuit,accurately predicting a failure rate has become difficult,if not impossible. Development of these critical components has conformed to Moore's Law,where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last two decades through reduction in transistor sizes creating faster,smaller ICs with greatly reduced power dissipation. Although this is great news for developers of high performance equipment,including consumer products and analytical instrumentation,a crucial,yet underlying reliability risk has emerged. Semiconductor failure mechanisms which are far worse at these minute feature sizes (tens of nanometers) result in higher failure rates,shorter device lifetimes and unanticipated,early device wear out.
Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae,industry accepted failure mechanism models,and device functionality can access reliability of those integrated circuits vital to system stability. Currently,four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration,Time Dependent Dielectric Breakdown,Hot Carrier Injection and Negative Bias Temperature Instability. Mitigation of these inherent failure mechanisms,including those considered wear out,is only possible when reliability can be quantitatively calculated. Algorithms have been folded into a software application to not only calculate a failure rate,but also give confidence intervals and produce a lifetime curve,using both steady state and wear out failure rates,for the integrated circuit under analysis. Furthermore,the algorithms have been statistically verified through testing,employ data and formulae from semiconductor materials (to include technology node parameters),circuit fundamentals,transistor behavior,circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address silicon-based integrated circuits of the 130 and 90nm technology nodes.
DfR is now working to extend the capability of the tool into smaller technology nodes (65nm and 45nm) and other material sets such as silicon on insulator (SOI). Several commercial organizations have indicated a willingness to assist with the development and validation of 45nm technology through integrated circuit test components and acquisition of field failure data. Continued development would incorporate this information and would expand into functional groups relevant for analog and processor based integrated circuits.
The initial work was performed by DfR Solutions,and funded by Aero Engine Controls,Boeing,GE,NASA,DoD,and FAA in cooperation with the Aerospace Vehicle Systems Institute (AVSI).

Continental is using the IPC solder spread coupon (adopted from NPL) to evaluate Pb-free solder pastes and PCB surface finishes for Solderability. This presentation will compare and contrast solder spread results for multiple PCB finishes using multiple Pb-free solder pastes. The spread data is collected for as-received PCBs and after one or more reflow processes to observe the degradation in spread for the different surface finishes. Very different behavior is observed when comparing common Pb-free compatible PCB surface finishes such as ENIG,OSP and immersion tin. Efforts to define specific pass/fail criteria for the solder spread coupon,based on comparisons to other common criteria,will be included. Additional information on the impact of variations in solder paste print volume to the resulting spread performance may also be presented if time/space allows. An overview of the results of the IPC 4-14 ENEPIG solder spread results may also be included if agreed to by the 4-14 committee.

European electronics industry is soldering with lead-free alloys for one decade now. In this period not only the knowledge of the alloys in the assembly process has been improved,but also a high amount of data is collected. Technology has changed over these ten years including the prices of the metal. The dramatic increase of operation costs due to high metal prices forces engineers to look more critical to their wave soldering process. Balver Zinn has been studying the consistency of alloys in wave soldering process since the implementation of lead-free. The lab measures the contamination of lead-free solder alloy samples of their costumers and thus enables them to do statistical process control on the alloy composition. In these ten years of lead-free soldering over 25.000 samples were investigated looking at contaminations of lead,the drift of the Copper content,and or increase of iron in the alloy due to solder pot erosion. Analyzing this data returns a lot of information on copper leaching for the different alloys. How to manage the copper level in the lead-free solder alloy to avoid an increase of soldering defects will be discussed. The data of these alloy analysis contains samples of all kind of production environments: low and high volumes,different solder machines and solder pot contents,solder temperatures,alloys,board finishes and inert systems versus soldering in air. With this presentation we try to give guidelines for the costumers how to control their alloy in order to minimize solder defects in combination with keeping the metal consumption/operational cost as low as possible.

The implementation of the European Restriction of Hazardous Substances (RoHS) Directive has initiated an electronics industry materials evolution. Printed wiring board laminate suppliers,component fabricators,and printed wiring assembly operations are engaged in numerous investigations to determine what lead-free (Pbfree) material choices best fit their needs. The complexities of Pbfree soldering process implementation insures a transition period in which Pbfree and tin/lead solder finishes will be present on printed wiring assemblies for many electronic product segments. One of the component surface finishes being offered by electronics industry component fabricators is 98% tin - 2% bismuth
(98Sn2Bi) as a Pbfree component finish option. This presentation documents an investigation of a solder joint integrity assessment of tin/bismuth component surface finishes in both tin/lead and Pbfree soldering processes under thermal cycle conditions. The investigation results are also compared/contrasted with other industry published data sets.

The implementation of the European Restriction of Hazardous Substances (RoHS) Directive has initiated an electronics industry materials evolution. Printed wiring board laminate suppliers,component fabricators,and printed wiring assembly operations are engaged in numerous investigations to determine what lead-free (Pbfree) material choices best fit their needs. The complexities of Pbfree soldering process implementation insures a transition period in which Pbfree and tin/lead solder finishes will be present on printed wiring assemblies for many electronic product segments. One of the component surface finishes being offered by electronics industry component fabricators is 98% tin - 2% bismuth (98Sn2Bi) as a Pbfree component finish option. This presentation documents an investigation of a solder joint integrity assessment of tin/bismuth component surface finishes in both tin/lead and Pbfree soldering processes under thermal cycle conditions. The investigation results are also compared/contrasted with other industry published data sets.

SAC105 was shown to have better drop shock reliability than SAC305 however SAC105 thermal cycle performance was not necessarily as good at SAC305. Small quantities (0.1% or so) of some elements appear to improve both drop shock and thermal cycle reliability of SAC105. This paper will be an overview of work performed to demonstrate this phenomenon.

With the release of IPC 7093,"Design and Assembly Process Implementation for Bottom Termination SMT Components," earlier this year,the term BTC is the newest acronym to enter the world of SMT. BTCs are very much like the BGAs but without the balls. Excellent electrical and thermal performance combined with lowest package cost has made this package very popular especially in mobile products. However,the absence of balls changes practically all aspects of design and manufacturing SMT assemblies using BTCs. The connection between the package and PCB is essentially like a postage stamp which poses challenges in both design and assembly of BTCs to achieve acceptable reliability. And achieving good yield is also a challenge since both the package and PCB must be perfectly flat. Any warpage in package and PCB has to be compensated by solder paste but too much paste creates voids and package floating and too little paste causes opens and insufficient solder resulting in premature failure. Based on the design and assembly guidelines in IPC 7093 co-chaired by the author,this presentation will focus on key issues in design and assembly to reduce defects and improve reliability.

Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size,such as a near die size footprint,thin profile,and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size,weight,electrical,and thermal properties are important. However,adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow,outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength,ductility,creep,and fatigue life In addition,voids could also produce spot overheating,lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area,large number of thermal via,and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations,a full thermal pad is desired for a low number of via. For a large number of via,a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad,the SMD system is more favorable than the NSMD system,with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessability,not by the shape. Voiding reduction increases with increasing venting accessability,although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.