Vern Solberg is an independent consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the industry for more than twenty-five years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication and furnishes the ‘Designers Notebook’ column for SMT magazine. Vern was also awarded the prestigious ‘Raymond E. Pritchard Hall of Fame Award’ and is currently an active member of IEEE,SMTA,IMAPS and the IPC,the industries standards development organization for electronics. Current IPC activity- Co-Chairman of the task group currently developing the IPC-7092,‘Design and Assembly Process Implementation for
Embedded Components’.

There is no issued industry standard for the workmanship of underfills – either from the perspective of visual examination (a la A-610) or by more intrusive techniques like cross-sectioning. This presentation will highlight what has been put together and submitted to the appropriate IPC standards committee for consideration. Further some challenges faced by trying to meet this standard may be delineated as
well.

The IPC Solder Products Value Council,in cooperation with iNEMI and a group of industry experts,has developed a protocol for testing the physical properties of lead free solder alloys. This presentation will review the status of the protocol’s development,the status of a round robin of the protocol’s test repeatability and then briefly discuss the prospect for developing better reliability models using creep data testing as described in the protocol.

Board-level designers are constantly expected to cram more computational power,into a smaller space,at lower cost,and accomplish this task in less time and with fewer resources. In this rush to meet customer requirements,common and costly hardware design mistakes are often made. Examples include part selection,component placement,board layout and specifications,and understanding the role design plays in ensuring long-term reliability. This presentation provides hardware designers with case studies of some common mistakes and the process by which these mistakes were inserted or overlooked during the design process. The presentation will also provide a checklist to avoid these mistakes,why these mistakes caused failures,and optimized corrective actions necessary to avoid these problems,but still ensure a successful product launch.

Electronic assembly innovations drive more performance using highly dense interconnects. Assembly residues may increase the risk of premature failure or improper functionality. The challenge for OEMs is to quantify safe residue levels and how residues impact long term reliability and functionality of hardware. To compound this problem,the question of “how clean is clean enough” is more challenging as conductors and circuit traces are increasingly narrower.
Highly dense bottom termination components decrease conductor pitch,spacing and standoff heights. The problem is that current spacing trends can yield spacing between printed circuit traces as small as 2 mils. As electrical fields rise,contamination at these narrower traces becomes more problematic due to voltage swings,high frequencies,leakage currents,and high impedance.
The purpose of this research is to build a new test board that provides a more accurate correlation and prediction of assembly residues to one or more aspects of long term reliability. The test board will be populated with a series of bottom termination components and cleaned. The research will follow a three phase strategy:
• Phase 1: PCB layout/Component Library Selection Geometries/Sample Size
• Phase 2 DOE Matrix: PCB Surface Finish,Flux & Cleaning Chemistries,Cleaning Systems/Analysis Techniques using IC,IR,HPLC,GCMS
• Phase 3 Conclusion: DFM approach for PCB designers layout relative to cleanliness limitations to establish a defined PCB design layout to facilitate an acceptable electrical measurement (i.e. fork,divider,capacitance,etc.) via a library of components (i.e.,QFN,PLCC,BGA,etc.) geometries to test cleaner/chemistries capabilities

Printed circuit board (PCB) material properties and surface roughness directly influence attenuation and NEXT/FEXT crosstalk signal integrity of high speed digital interconnect design. Balancing performance,cost,and ease of fabrication requires a quantitative understanding of the impact that the dielectric material and surface roughness will have on the performance of the signal path through gigabit PCBs,backplanes,cable assemblies and connectors. An in-depth understanding of how the material will perform when used to fabricate 25+ layer count boards with thicknesses over 250 mils is required. This paper provides a survey of these problems and of possible measurement solutions,including characterizing signal path integrity,power/ground integrity,materials properties,package/fixture measurement challenges and the surface roughness of copper signal traces.

In this evaluation we will show an ionic residue comparison using Umpire 2 boards that were top and bottom surface mounted with standard reflow and selective wave soldered on the connector and B-24 comb patterns. For this evaluation,30 boards were processed using a no clean flux with lead-based soldering parameters. Three groups were evaluated,Group A (not cleaned),Group B (water only cleaned) and Group C (saponified steam cleaned). The 30 assemblies and 3 unprocessed boards were SIR tested for electrical performance and then each assembly was C3 tested in three locations (0.1 in2 area) and then the entire board was bag extracted.

Counterfeit and substandard parts and components have been a recurring theme in practically every market. For the last several years,the largest concern has been in the military and aerospace industries. Many of these re-marked and recycled parts are coming back into the US from electronic waste that was sent overseas. In an attempt to mitigate risk and potentially eliminate use of counterfeit and substandard parts,it is important to develop a counterfeit inspection procedure for incoming materials. This inspection can be as basic as a visual examination but becomes more successful at identifying potential counterfeit components and parts when a few more techniques that are advanced are employed. This webinar will present background regarding the counterfeit market as well as provide information on various tests and testing techniques for identification of counterfeit parts.

The breadth of materials and processes used in today’s electronic assemblies may make it impossible to predict SIR/ECM performance without adequate testing of material and process combinations. Some materials behave very well when tested singularly,yet behave very poorly when used together. This is of great importance as most possibilities coexist on real-world industry product. This presentation will provide a survey of actual results with broad,non-brand specific categories of materials and process combinations. Some trends will be presented to help the audience appreciate areas of possible concern.

High yields in the stencil printing process are essential to a profitable SMT assembly operation. But as circuit complexity continues to increase,so do the challenges of maintaining a successful solder paste deposition process. To help assemblers address the challenges presented by evolving technologies,stencil suppliers have provided a variety of options in stencil technology,including new foil materials,manufacturing processes and coatings.
A study was undertaken to quantify the effects of stencil material on paste deposition in high volume production processes. The experiment focused only on laser cut stencils,and compared the typical stainless steel,non-electro polished foils with electro polished stainless steel,fine grain stainless steel,and electroformed nickel. The DOE strived to maintain consistency of all other variables involved in the process,changing only the stencil material. The test vehicle design varied theoretical area ratios from 0.50 to 0.75 in 0.05 increments (actual area ratios varied between 0.48 and 0.77). Output variables were paste deposit volumes,which were expressed as transfer efficiencies based on measured (actual) aperture volumes.
The transfer efficiencies of the four materials are compared and performance differences are discussed. High magnification photographs of the aperture walls provide visual images of the wall topographies. The effect of electro polishing is shown and discussed.