The electronics industry could benefit greatly from using a reliable, manufacturable, reduced temperature, SMT solder material (alloy-composition) which is cost competitive with traditional Sn3Ag0.5Cu (SAC305)solder. The many possible advantages and some disadvantages / challenges are discussed. Until recently, the use of Sn/Bi based materials has been investigated with negative consequences for high strain rate (drop-shock) applications and thus, these alloys have been avoided. Recent advances in alloy “doping” have opened the door to revisit Sn/Bi alloys as a possible alternative to SAC-305 for many applications.  We tested the manufacturability and reliability of three low-temperature and one SAC-305 (used as a control) solder paste materials. Two of these materials are doped Sn/Bi/Ag and one is just Sn/Bi/Ag1%.We will discuss the tests and related results. And lastly, we will discuss the prospects, applications and possible implications (based on this evaluation) of these materials together with future actions.

Keywords: Bismuth, Tin, LTS, SMT, Paste, Low Temp Solder.

With the adoption of Wafer Level Packages (WLP) in the latest generation mobile handsets, the Printed Circuit Board (PCB) industry has also seen the initial steps of High Density Interconnect (HDI)products migrating away from the current subtractive processes towards a more technically adept technique, based on an advanced modified Semi Additive Process (amSAP).

This pattern plate process enables line and space features in the region of 20um to be produced, in combination with fully filled, laser formed microvias. However, in order to achieve these process demands, a step change in the performance of the chemical processes used for metallization of the microvia is essential.

In the electroless Copper process, the critical activator step often risks cross contamination by the preceding chemistries. Such events can lead to uncontrolled buildup of Palladium rich residues on the panel surface, which can subsequently inhibit etching and lead to short circuits between the final traces.

In addition, with more demands being placed on the microvia, the need for a high uniformity Copper layer has become paramount, unfortunately, as microvia shape is often far from ideal, the deposition or “throw” characteristics of the Copper bath itself are also of critical importance.

This “high throwing power” is influential elsewhere in the amSAP technique, as it leads to a thinner surface Copper layer, which aids the etching process and enables the ultra-fine features being demanded by today’s high end PCB applications.

This paper discusses the performance of an electroless Copper plating process that has been developed to satisfy the needs of challenging amSAP applications. Through the use of a radical predip chemistry, the formation, build up and deposition of uncontrolled Pd residues arising from activator contamination has been virtually eradicated. With the adoption of a high throwing power Copper bath, sub 30um features are enabled and microvia coverage is shown to be greatly improved, even in complex via shapes which would otherwise suffer from uneven coverage and risk premature failure in service.

Through a mixture of development and production data, this paper aims to highlight the benefits and robust performance of the new electroless Copper process for amSAP applications.

The demand for miniaturization and higher density electronic products has continued steadily for years and this trend is expected to continue,  according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified Semi-Additive Process (mSAP), uses a thin base copper layer made by pre-etching.  The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine pitch circuitries.

A novel catalyst system, liquid metal ink (LMI),has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI)to wafer level packaging substrates and enabling 5micron level feature sizes. This novel catalyst has a unique feature, high density and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage, while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP process.

This paper discusses this new catalyst process which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and the conventional SAP PCB process.

Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wire bond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss was due to nodules and scratches on the wire bonding pads.

The PCB manufacturer attempted to eliminate nodules and scratches. First, a light scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire bonding pad, the board was still considered a reject. In order to reduce scratches on wire bonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable.

Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches, and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to find out the effects of nodules and scratches on wire bonds. The dimension of nodules including height, and the size of scratches including width were measured prior to wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds were conducted using wire pull tests before and after reliability test. Based on the results of the wire bonding evaluation, the internal specification for nodules and scratches for wire bondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation, compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.

This paper examines the development and classification of flexible and stretchable conductive pathways to carry power and data and details the technical challenges as well as the methodologies deployed to develop a robust and commercial solution. Along with the technological advancements in the last 20 years, there has been a marked growth in the functional needs to be added to apparel. Market demand today is creating a new and evolving need for soft good integrations into a portfolio of product categories, creating with it the need to develop soft circuitry and connectivity technologies applicable to apparel/textile form, without limiting the traditional textile properties. Key to this is the capability to develop suitably specified conductive pathways whilst retaining properties such as stretch, bend, drape, breathability and offer fabric like appearance in a cost effective and sustainable manner. Herein, reviewed is the mass manufacturing of narrow fabrics and bondable data lines with the capability in transferring data from low frequencies(KHz range) to extremely high frequencies (GHz range); conductive path resistances that can range from a few ohms per meter to tens of milliohms per meter; along with stretch-ability of up to and beyond 100%. Also discussed are the methods for testing and validating these conductive circuitries including laundering, mechanical and environmental reliability; and the classification of the conductive circuitry methodologies based on the e-textile applications that can make most use of different attributes of these methods.

The advent of electronic materials with the potential to undergo extreme deformation while maintaining conductivity has led to the development of advanced stretchable electronic systems. These systems have applications in vital industries ranging from consumer products to medicine and defense. Of interest are flexible, stretchable, wearable electronic (FSWE) systems that employ flexible and/or stretchable substrates, conductive materials, dielectrics, etc., to achieve the requisite flexibility and stretchability to conform to complex shapes. Thus, there is a need to quantify the mechanical and electrical performance and reliability of FSWE devices under such deformed use-case loading conditions. Several mechanical tests have been developed by various researchers to understand the performance and reliability of such devices under stretching, bending, twisting, and folding conditions. In this paper, a different mechanical test method is discussed in which a printed element on a thermoplastic polyurethane (TPU) substrate is mounted onto an inflatable bladder of known geometry to induce multiaxial strains and the in-situ electrical resistance of the printed element is measured during inflation. This test will hereafter be referred to as the Bladder Inflation Stretch test for FSWE devices, or the BIS test. Stretchable screen-printed silver ink traces cured onto TPU is chosen in this study due to its common use in wearable devices. A bladder geometry with variable radii of curvature is employed to simulate a variety of anthropomorphic geometries (i.e. the flexure of a bicep, the bending of a knee, etc.). Both monotonic and cyclic loading regimes are employed to determine electrical resistance change of a Serpentine and a Spiral printed trace. The measured electrical resistance values are compared against the data available in open literature.  Recommendations are made for extending the BIS test set up to study other phenomena related to the reliability of wearable electronics.

The paper will discuss the integration of 3D printing and inkjet printing fabrication technologies for microwave and millimeter-wave applications. With the recent advancements in 3D and inkjet printing technology, achieving resolution down to 50 um, it is feasible to fabricate electronic components and antennas operating in the millimeter-wave regime. The nature of additive manufacturing allows designers to create custom components and devices for specialized applications and provides an excellent and inexpensive way of prototyping electronic designs. The combination of multiple printable materials enables the vertical integration of conductive, dielectric, and semi-conductive materials which are the fundamental components of passive and active circuit elements such as inductors, capacitors, diodes, and transistors. Also, the on-demand manner of printing can eliminate the use of subtractive fabrication processes, which are necessary for conventional micro-fabrication processes such as photolithography, and drastically reduce the cost and material waste of fabrication. The utilization of 3D and inkjet printing to fabricate integrated circuits interconnects and antennas is an interesting avenue for research due to the customized nature of certain applications such as automotive radar and 5G wireless solutions. This paper will explore different ways of interfacing with monolithic microwave integrated circuits (MMICs) using additive manufacturing methods including printed vias, ramp interconnects, and wire bonds. With these structures, microwave properties such as matching and losses can be improved due to the ease of printing tailored interfaces that match with each individual device. It will also include demonstration of fully additively-manufactured antennas exhibiting excellent bandwidth and circular polarization, something that is expensive and difficult to achieve with traditional manufacturing methods. Finally, the paper will also introduce future directions for additively-manufactured electronics, including the packaging of high-power devices, cooling functionality, and using exotic materials for electromagnetic interference shielding and flexibility.