Many different final plated finishes are used in the PCB industry, each with its own influence on insertion loss. The impact of an applied finish on insertion loss is generally dependent upon frequency, circuit thickness, and design configuration. This paper will evaluate the effects of final plated finishes on the insertion loss of two popular high-frequency circuit design configurations, microstrip transmission- line circuits and grounded coplanar-waveguide (GCPW) transmission-line circuits. Data will be presented for loss versus frequency for six different plated finishes commonly used in the PCB industry, and opinions will be offered as to why the loss behavior differs for the different plated finishes and for the different circuit configurations. Because the insertion loss of high-frequency circuits is also dependent upon substrate thickness, circuits fabricated on substrates with different thicknesses will be evaluated to analyze the effects of substrate thickness on insertion loss using different plated thicknesses.

This report will also explore many different aspects of final plated finishes on PCB performance. The nickel thickness in electroless-nickel-immersion-gold (ENIG) finishes normally has some variations; data will show the effects of these variations on the RF performance of a PCB. Immersion tin is often used to minimize thickness variations and analysis will show the effects on RF performance for different thicknesses of immersion tin. The effects of plated finish on PCB performance can vary widely over frequency, and those effects will be shown for a wide range of frequencies, from 1 to 100 GHz.

Conventional Electroless Nickel/Immersion Gold (ENIG) currently available in the market is prone to brittle solder joints failures. Due to these reasons, there are field failures and reliability concerns of electronic assemblies - component disconnection which lead to overall malfunction of electronic assemblies. The novel ENIG achieves robust solder joints and provides improved quality and reliability of electronic assembly. Also, it uses cyanide-free chemistry for the immersion gold process making it eco-friendly. This allows manufacturers to consume eco-friendly product while avoiding major field failures and resulting consequences.

With conventional ENIG, the immersion gold process operates on galvanic displacement process (displacing Ni atoms by Au atoms). If not controlled properly, the displacement can be aggressive leading to Ni corrosion, commonly known as “black pad” or hyper-corrosion of Ni. This leads to brittle solder joints failures. Also, during the reflow process the gold layer dissolves into solder and intermetallics form between tin and nickel. In conventional ENIG intermetallics, too much nickel diffuses into tin leaving behind soft Ni3P layer at the interface. This soft layer is responsible for brittle solder joint failures. The novel ENIG employs an interfacial engineering approach which leads to 10X corrosion resistance of Ni surface helping to prevent black pad/hyper-corrosion. Also, it creates a barrier for Ni atoms to diffuse too much in tin forming distinct-thin intermetallics which are robust and eliminates brittle solder joints failures. Ball Shear and Ball Pull tests (Industry Standard Based testing: JESD22-B115 and JESD22-B117) have been conducted after (1, 3 and 6) reflow cycles during the soldering process. Also, as a part of simulating aging and evaluating long term reliability of solder joints/electronic assemblies, samples were subjected to 150°C for 500 hours and 1000 hours before conducting Ball shear test and Ball Pull test. The novel ENIG board surface finish achieves robust solder joints for better reliability of electronic assemblies.

The majority of flexible circuits are made by patterning copper metal that is laminated to a flexible substrate, which is usually polyimide film of varying thickness. An increasingly popular method to meet the need for lower cost circuitry is the use of aluminum on Polyester (Al-PET) substrates. This material is gaining popularity and has found wide use in RFID tags, low-cost LED lighting and other single-layer circuits. However, both aluminum and PET have their own constraints and require special processing to make finished circuits. Aluminum is not easy to solder components to at low temperatures and PET cannot withstand high temperatures. Soldering to these materials requires either an additional surface treatment or the use of conductive epoxy to attach components. Surface treatment of aluminum includes the likes of Electroless Nickel Immersion Gold plating (ENIG), which is extensive wet-chemistry and cost-prohibitive for mass adoption. Conductive adhesives, including Anisotropic Conductive Paste (ACP), are another alternate to soldering components. These result in component-substrate interfaces that are inferior to conventional solders in terms of performance and reliability. An advanced surface treatment technology will be presented that addresses all these constraints. Once applied on Aluminum surfaces using conventional printing techniques such as screen, stencil, etc., it is cured thermally in a convection oven at low temperatures. This surface treatment is non-conductive. To attach a component, a solder bump on the component or solder printed on the treated pad is needed before placing the component. The Aluminum circuit will pass through a reflow oven, as is commonly done in PCB manufacturing. This allows for the formation of a true metal to metal bond between the solder and the aluminum on the pads. This process paves the way for large scale, low cost manufacturing of Al-PET circuits. We will alsodiscuss details of the process used to make functional aluminum circuits, study the resultant solder-aluminum bond, shear results and SEM/ EDS analysis.

Constant increases in feature density of printed circuit board assemblies (PCBA) has highlighted the importance of functional circuit test (FCT) systems in a manufacturing process. Automated FCT has traditionally been an expensive and complicated aspect of a product development, and it often requires significant engineering time to develop. This development cost rises as more features are added. In this paper we present simple methods to reduce FCT development time and cost through the use of modular fixtures and with fully integrated test equipment. These methods have reduced capital costs by up to70% and reduced fixture development time by unto50%. Additionally, we present modern design techniques and considerations which, when combined with modular fixtures improve FCT reliability, ease replication, and increase operational efficiency in high-mix, low-to mid-volume manufacturing test environments.

IoT and 5G applications have theirchallenges when it comes to functional testing –especially for the probing part inside a functional test fixture(hereinafter referred to as “FCT” fixture).In this paperwe would like to demonstrate how to successfully use passive coaxial probes for power level and other tests of IoT and 5G devices. Data rates are fast and especially for 5G frequencies can be pretty high up in the GHz range which makes the use of conventional spring-loaded probes very difficult if not impossible (very short fine-pitch probes or on-wafer architectures would need to be used). Design engineers, production line engineers and test probe manufacturers must work hand in hand for a successful end-of-line test.

For IoT applications, the manufacturers are further challenged with a need for low-cost test probes which poses a risk because cheaper test solutions quite often are not well impedance-defined which could add additional losses to the test –and worst-case lead to false errors. For 5G applications the cost is not the main driver but traditional spring-loaded concepts sometimes would not work at all for more critical measurements –the higher the frequency the greater the impact of mechanical properties is on the electrical performance.

We present a holistic concept for using test probes for these applications and focus on various different topics such as design for test, RF probing challenges, ideas to manufacture probing solutions at a rather low cost, usage of novelty non-conductive probes and its benefits over regular conducted testing and so on. The paper will be of interest for many different groups. The audience will learn how to select more economy priced but high-quality parts for IoT testing, PCB design engineers will learn how to successfully lay out test points for RF probing and production line test engineers will learn which RF probing concepts are out there already and what is being worked on “behind the scenes”.  Please note that we will not discuss any “Over-The-Air” (OTA) technologies in detail but focus on conducted testing for the presented applications.

There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second(Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument calleda synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and “synthesized” into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0(running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.

Microvias connect adjacent copper layers to complete electrical paths. Copper-filled microvias can be stacked to form connections beyond adjacent copper layers. Staggered microvias stitch adjacent copper layers with paths that meander on the layers between the microvias. Both microvia configurations are formed by essentially the same sequential operations of laser drill, metallization, and patterning, using various chemical, mechanical, and thermal treatments to form each layer, one over the other. Stacked microvias must be filled while staggered microvias do not. Process specifics differ manufacturer to manufacturer. Stacked microvias fracture while staggered microvia do not during reflow assembly. Assembly reflow subjects the printed wiring board (PWB) to the greatest temperature excursion. Stacked microvias with a weak interface fracture during assembly reflow and are a hidden reliability threat. This phenomenon was reported in IPC-WP-0231 in May of 2018. IPC-TM-650 Method 2.6.27A is a performance based PWB acceptance test that detects fractured microvias. SEM pictures are presented to initiate discussions in the search for root cause. Included are cross-section pictures of completed microvia structures, SEM pictures after laser drill, and after electroless copper. Not all stacked microvias fail. To learn why, microvia samples were collected from different PWB suppliers. Microvias drilled by UV lasers are compared to microvias drilled by other laser configurations. The pictures show that microvia structure was influenced by laser type. This paper discusses the various laser drilled microvias and presents SEM photographs to begin the search for the root cause of weak copper interface.