The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures.  Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable.  The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for are riable PWB.  Minimum copper wrap plating thickness has become an even a bigger  concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design.  PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching.  The companies started a project to study the relationship between Copper wrap plating thickness and via reliability.  The project had two phases.  This paper will present findings from both Phase 1 and Phase 2.

This paper introduces structural electronics technology enabling smart molded structures. It also presents a case for developing industry standards specific to structural electronics materials, processing and testing.  In the first part, we outline the benefits of structural electronics technology as well as the manufacturing processes. Smart molded structures are made by integrating and encapsulating printed electronics and standard electronic components within durable,3D injection-molded plastics. Structural electronics technology and processing differs significantly from conventional electronics. Thus, we describe how these differences influence component and materials certification for use within injection molded plastics. In the second part of the paper, we discuss the lack of suitable standards for structural electronics. Two technologies, bearing a resemblance to structural electronics, have standards. However, they do not cover all aspects and we see a need for further development.

Flexible hybrid electronics (FHE) refer to a category of flexible electronics that are made through a combination of traditional assembly process of electronic components with the high-precision ink printing technologies.  By integrating silicon components with printed inks and flexible substrates, FHE will revolutionize the IoT and wearable industries. With FHE, designers can create a heterogeneous electronic system that can be fully integrated with different sensors, lighter in weight, more cost effective, more flexible and conforming to the curves of a human body or even stretchable across the shape of an object or structure—all while preserving the full functionality of traditional electronic systems.  However, many challenges remain. Industry is still at the early stage of developing and implementing FHE systems. A variety of design, assembly and reliability issues need to be evaluated and addressed. This paper will discuss these challenges and present a case study of making and evaluating FHE systems.

Key Words: Flexible Hybrid Electronics, FHE, Flexibility, Stretchability, Wearable, Printed electronics, Conductive ink.

Inherent variation among human brains causes difficulty in the design of electroencephalography (EEG)-enabled universal brain-machine interfaces (BMI). Existing EEG systems suffer from inconsistent signal quality, while requiring many rigid wires and metal electrodes on a hair cap. Although recent machine learning techniques offer a simpler EEG arrangement with fewer electrodes, these EEG devices still involve intrusive and heavy headgear, equipped with separate non-portable electrical hardware. Here, we introduce a fully portable, wireless, flexible hybrid system on a soft elastomeric membrane, which represents an ergonomic, comfortable, long-term wearable BMI. Additive manufacturing, based on aerosol jet printing, fabricates an ultrathin, open mesh electrode that can be mounted on the skin for biopotential recording, while a wireless electronic circuit is manufactured by the combination of material transfer printing and hard-soft materials integration. These imperceptible soft electronics incorporates a nanomembrane electrode on non-hair-bearing skin, flexible electrodes on hair-bearing scalp, and flexible circuit on the neck for wireless data acquisition. Analytical and computational studies of materials and mechanics establish the fundamental design criteria of the flexible, skin-like hybrid electronics (SHE), which enables seamless, portable EEG recording with significantly enhanced signal quality over commercial systems. With six human participants, this portable system achieves the most efficient information transfer rate (111.75 ± 1.15 bits per minute per channel). An in vivo demonstration of the SHE-enabled BMI shows precise, low-latency control of a wireless wheelchair via two-channel EEG.

The technical and economic benefits derived from lowering the reflow temperatures have motivated the evaluation of new Sn-Bi low temperature alloys for soldering. Eutectic Sn-Bi alloy is usually described as having a brittle nature, not being able to sustain mechanical shock and thermal cycling stresses as well as Sn3Ag30.5Cu (SAC305)solder. A new non-eutectic Sn-Bi solder with 2 wt.% additives(generally called here as alloy A) is evaluated here and compared with other eutectic Sn-Bi alloys and SAC305.Tensile tests at -55oC, -25oC, +25oC, +75oCand +125oC were performed to provide insights on their relative mechanical properties. Mechanical drop shock tests of BGA84 and LGA84 were performed as pertheJESD22-B111 standard, while thermal cycling tests were performed from -40oC (10 min) to +125oC (10 min) as per the IPC 9701 standard. The BGA84 was used for thermal cycling in situ monitoring, while BGA169, SOT223, QFP44 and 1206 chip resistors were also used for evaluating the effect of thermal cycling on IMC thickness, shear strength and tin whiskers. The results show that, for the aforementioned packages, assembly and testing conditions, alloy A is a viable replacement for SAC305. The joints formed with alloy A have the mechanical (drop) shock and thermal cycling performance as good as, or, in some cases, better than the same joints formed with SAC305.

Key words: lead-free, low temperature soldering, thermal cycling, mechanical drop shock, shear strength, tin whiskers.

Sn3Ag0.5Cu (SAC305)is the major solder alloy after RoHS was adopted by the European Union. Since its melting temperature is relatively higher than eutectic SnPb alloy, the peak reflow temperature increases. This transformation in the assembly industry impacts the component requirement, where the deformation probability (warpage) of a flat component is increased, which impacts the production yield. A lead-free, low-temperature SMT solder is needed to resolve this dilemma.

Low-temperature SMT assembly refers to the reflow process with a peak temperature less than 200°C. The new process provides a few advantages like reducing energy consumption, reducing BGA component warpage during reflow and diminishing non-wetting open (NWO) and head-on-pillow (HoP) defects. The SnBi alloy is one of the candidates used in low-temperature SMT assembly. However, the brittle mechanical property of conventional SnBi alloys will degrade the reliability of the assembly. The SnBi alloy properties can be altered via several means.

In this paper, the roles of additive and bismuth content will be discussed. Eutectic SnBi and three newly designed SnBi-based alloys (Sn57Bi1AgX, Sn48Bi1AgX and Sn40Bi1AgX, X represents <0.5wt.%of additive element) were experimented upon. Solder pastes that were blended with the aforementioned alloys and flux were used to assemble on the PCB with BGA components that have SAC305 solder spheres pre-mounted. The same reflow profile was used for all pastes. Cross-sectional analysis, shear testing, drop testing and thermal cycling testing were conducted to determine the microstructure, shear force, drop reliability and thermal reliability. The results show that the microstructure, especially the bismuth-rich phase, became finer and the shear force was elevated when the additive was added. On the other hand, the drop reliability improved with decreasing bismuth content, and the thermal reliability improved with increasing bismuth content.

The world as we know it is changing. Electronic megatrends are impacting the world and rapidly changing the way we experience day-to-day life. The imminent 5Gwireless infrastructure will be a critical enabler for so many electronics megatrends, including autonomous vehicles, the Internet of Things (IoT), big data storage farms, artificial intelligence (AI)and AR/VR.5Gisalsoprojected to deliver faster data rates at 100Xhigher frequencies and with over 1000X more data traffic and will require novel manufacturing solutions for mm Wave length signals, and far higher levels of signal integrity and impedance control than ever before.  The major trends that are driving more accurate, efficient and smart production equipment are smartphones, automotive, 5G, data storage, and Industry 4.0.

This paper highlights changes in PCB technologies such as advanced high-density interconnect (HDI)PCBs–also referred to as Substrate-Like PCB–and flex PCBs, and the need to focus on tighter impedance control for mm Wave signals and production data traceability and analysis.  All of these industry trends have generated the need for new PCB production solutions focused on inspection, measurement, metrology and data traceability and analysis.

This paper presents assembly challenges of mixed area array technologies covering Very Thin ChipArray® Ball Grid Array (CVBGA) and its Land Grid Array version (CV-LGA), embedded Wafer Level Land Grid Array (eWLP-LGA), and Copper-Pillar Flip-Chip (CP-FC) die—all with daisy-chain patterns to enable thermal cycle reliability monitoring for solder-joint failure evaluation. Twenty-seven (27) PCBs were assembled with a large number of variables in the design of experiment (DOE) to address: (1) assembly of mixed die and die-size array, (2) the effect of daisy-chain patterns on top layer or second layer bymicrovia-in-pad connections, (3) the effect of underfilling on improving resistance to thermal cycling, (4) challenges of single--and double-sided assembly processes, and (5) the effect of double-sided assembly on thermal cycle reliability. Acceptable assemblies with and without underfill were subjected to thermal cycling between –40°C and 125°C for solder-joint reliability characterization and failure-mechanism assessments. The paper will present details of DOE assembly parameters with the status of thermal cycle evaluation.

KEY WORDS: ball grid array, BGA, chip array BGA, embedded wafer level package, eWLP, land grid array, LGA,

Board level reliability testing is becoming a requirement amongst users for acceptance of components and packages. Standard component level JEDEC tests are not sufficient to qualify a supplier, this must be accompanied with board level reliability data to ensure assembly and field reliability. The paper presents a summary of board level reliability test performed on RF packages, the assembly process controls and monitoring, mechanical and environmental reliability tests, understanding of failure modes and lessons learned.