Uniformity of Nickel Plating Thickness in High Aspect Ratio Plated Through Holes

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Nickel plating is often used on PWBs to increase wear resistance and to prevent diffusion between copper and other plated metals. The nickel plating is often present in through holes as well as on the surface,such as when the entire PWB panel is nickel/gold plated or when press fit pins are used for assembly. When the plated through holes are evaluated by microsectioning,it often becomes apparent that the nickel plating is not uniform. It tends to be much thinner in the middle of the hole than on the surface of the board,and may not meet minimum thickness requirements. This paper will evaluate the effect of various plating parameters and chemical additives on through hole plating uniformity. Data will be presented comparing direct current and pulse plating. This paper will also evaluate how the addition of chemical additives to increase throwing power affects the intrinsic stress and grain structure of the nickel. Tests include plating PWBs having through holes of varying diameters and aspect ratios with nickel in thicknesses up to 100 mils. Nickel thickness and uniformity are evaluated both by microsection and X-ray fluorescence measurement techniques.

Author(s)
David M. Lee,Frank I. Collins,Ann E. Dietrich,John T. Folkerts,Walter A. Johnston,Richard J Saunders
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Processing High Density Interconnects: Selecting the Best Option for Via Fill Applications

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With the increased use of High Density Interconnects in printed wiring boards (PWB) there is a critical need for reliable methods to completely fill through hole and blind vias. Complete filling of the vias is often necessary to prevent solution entrapment or failures during thermal cycling. For double sided and multilayer printed wiring boards,complete filling of through holes and blind vias include the use of conductive and non-conductive polymeric ceramic filled paste materials,and the occasional use of liquid photoimageable soldermasks (for partial via filling) For blind vias at n-1,superfilling of the via with copper plating is also gaining acceptance in the market place. In addition,methods to fill buried vias include the use of filling with resin during lamination or the use of the polymeric pastes described above. Blind vias within a sublam can be filled via copper plating as well. The best option depends upon via diameter,via depth,productivity and reliability requirements. In recent years plating of microvias and using ceramic-filled plugging paste for buried vias has gained popularity. The purpose of this paper is to discuss the applications,advantages and disadvantages of each option and offer guidelines for selection of the process that will best suit the needs of the board manufacturer. Applications involving copper electroplating and ceramic plugging pastes will be discussed in detail. We will evaluate thermal stability of the vias using Interconnect Stress Testing (IST).

Author(s)
Michael Carano,Bill Bowerman,Lee Burger
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Development of Micro Drill Bit for Drilling Environment-Friendly PCBs

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Currently environment-friendly PCBs (including lead-free assembly compatible PCB and halogen-free PCB) become popular in PCB industry to meet the requirements of environmental protection. Correspondingly,as a fundamental manufacturing process in PCB fabrication,mechanical drilling has to be innovated. A new type of drill bit is developed to provide solutions for drilling environment-friendly PCBs.
Worldwide PCB and micro drill bit manufacturing industry are briefly reviewed first. Challenges of drilling environment-friendly PCBs are described and the objective of this study is covered. Then key design points including helix angle design,primary face angle design and helix groove shape optimization are presented. The influential mechanism of drill bit key parameters on its rigidity,strength,debris evacuation capability is investigated. Helix angle,helix groove shapes and primary face angle are optimized to ensure sufficient cutting edge strength and excellent wear-resistant capacity. Finally,experiments are conducted to verify the performances of micro drill bit with optimized parameters. Experimental results confirm that a micro drill bit with small helix angle and primary face angle as well as optimized helix groove shape is beneficial to drilling environment-friendly PCBs.

Author(s)
Lianyu Fu,Fan Yang
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Tools & Methods for Lean Production Management in EA

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Lean manufacturing is far from a new concept,and many within the Electronics Assembly (EA) industry are already familiar with the principles and concepts behind it. However,in spite of widespread understanding,the percentage that actually “Live Lean” within EA tends to be far less.
If “Lean” offers such a compelling business advantage,one must critically ask why it has not yet been adopted widely and successfully to date in the “Leading Edge” EA industry? Fortunately today,several technologies and tools available to the EA industry offer new possibilities to realize a major impact as never before.
The intention of this conference paper is to examine some of the new developments in Lean Production Management in EA. Included is a brief look into Lean Production Management concepts such as the coordinating the “Value Stream” supplying products according to customer demand. Lean Production Management can be viewed as “real-time execution-based scheduling” and can keep the factory activity in perfect synchronization with minimum effort.
For high-mix EA operations this paper will also introduce “capacity-driven” beside the “inventory-driven” methods whereby supplying processes are triggered to produce the next item needed when capacity becomes available in downstream processes.
An important consideration of Lean Production Management is effective control of material levels and WIP (Work In Process). Using various methods for tracking and control provides the ability to highlight “Hidden” problems,and with visibility – further enables one in continuous improvement of the production system.
This paper considers tools and technologies available to assist in institutionalizing Lean Production Management. A discussion of a case study is included.

Author(s)
Tuan Nguyen,Vern Harrison
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Standardized Traceability Ratings for Manufacturing

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Traceability and process control are no longer requirements reserved for manufacturers in regulatory or specific market segments. Today,all manufacturers who aspire to achieve or to maintain a ‘world class’ status must deliver some degree of traceability. The PCB assembly industry lacked a common language regarding the nature of traceability or its levels. Nor has there been a means to benchmark such capability or to communicate its nature to customers or regulatory agencies in a common manner.
Recently,we,in collaboration with a leading supplier of dummy components and process testing kits,partnered together to offer an innovative kit designed to validate and benchmark the entire manufacturing process and provide the potential for rich product and process traceability detail. This new kit provides the physical materials and the procedural guide to determine a factory’s traceability and control capability,and then rate the results in a formalized matrix. These ratings can be used to demonstrate capabilities,communicate to customers or auditors,or to provide a start point for manufacturers to improve their capabilities and track progress along the way.
This materials kit and ratings methodology aids manufacturers the demand-side of the market in the following ways:
- Benchmark Traceability and Control
Test and validate three key elements of traceability; exercising quality manufacturing practices control mechanisms to assure process execution of these practices is proper even under high-change conditions,and the resultant reporting scope and depth that serve as evidence of the practices and controls performed. This approach of validating process control and visibility yields a comprehensive assessment of a factory’s capabilities.
- Communicate Capabilities
Using both the elements of the methodology and the metrics derived from an audit when it is applied,manufacturers have the means to convey to their customers or auditors their true traceability capability. In the past,this has been impossible without a common rating system or even a generalized agreement on the maximum range of what traceability entails. The purpose of this kit is to establish a common rating on the scale from simple traceability to world class capabilities. The scale can then be used to communicate a factory’s capabilities in a uniform manner to management and external parties that require this information.
- Improve What is Measured
The rating scale aids manufacturers who are continuously looking for ways to improve their factory operations. Through uniformed measurements,a road map can be developed to advance a plant’s manufacturing processes,controls,and traceability. By measuring a factory’s capabilities today,this kit aids in defining path to the future.
- Technical Basis
Aegis’ methods of rating traceability have been concurrently developed with,and adopted by,many of the leading manufacturers in the industry. The collective challenges and experiences of a customer base exceeding 1000 corporations on five continents have contributed to the scope of the methodology. Users of the method and kit consequently benefit from over seven years of definition and usage in factories all over the world to rate systems and processes against this scale.

Author(s)
Robert Miklosey
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Prisma - A Novel PCB Engineering Software

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Prisma is a PCB-Engineering software developed by DYCONEX AG,Switzerland (manufacturer of PCBs). Compared to existing solutions on the market it allows for broad standardization of the process flow while not imposing any restrictions on the design. It is a platform to specify the build-up,materials and the complete work instructions for PCBs. Engineers transform the customer data into full manufacturing papers by means of Prisma. The software has been developed for company internal use only and is (currently) not being sold. One of the key features of Prisma is its freely definable library of process modules. These modules always reflect the current capabilities and process settings. Existing products can be compared to the current state of the module library und be updated in a semi-automatic way. Build-ups and operation plans are presented in an interactive graphical screen that allows the engineer to build the product and incorporate changes in an easy and intuitive way without the need to take care of the detailed process specifications. In addition to formatted easy readable work instructions,Prisma returns schedule- and cost relevant operation times for each process allowing a quick and precise cost estimate for quotations. The software includes an automatic revision management complying with the high traceability requirements of customers working in the medical and military sector. Access to data is restricted by user login. The software is based on SQL Server and .NET technology and includes an interface to the ERP-systems (Enterprise Resource Planning) Abacus and Microsoft Dynamics AX. Live access to the material,product and customer database kept in the ERP-system guarantee always current data. Production planning and costing are accomplished in the ERP-system based on data provided by Prisma.
Introduction
Printed Circuit Boards are manufactured in a long chain of processes,each of which can have several parameter settings. A typical operation plan for a PCB consists of 50 to 300 single processes. Most processes are critical,meaning that they can not be omitted without leading to a non functional or lower quality PCB. A certain design does not lead to a unique process chain however. There always exist optional processes or groups of processes as well as alternative process blocks. Which of these alternatives is chosen may influence yield,costs and quality of the product. The requested quality level - e.g. the extents of AOI and visual inspections being planned - is primarily given by the customer (specification,IPC level) and the standards of PCB manufacturer (defining that certain tests are done even if not requested by the customer). Optimization of yield and costs is an essential key in gaining competitive advantage,allowing lower target prices. Raising the yield of a product from 80% to 90% reduces its costs by 1/9. If this can be achieved by simplifying the operation plan,one can easily gain significant cost reduction without implementing new technologies or changing the build-up. Optimization itself has its costs,since it usually involves engineering capacity. Our company manufactures around a hundred different PCBs at a time making it next to impossible to optimize each of these products. The idea here is to automate the optimization process,or better still to start with a near optimum design and apply optimizations of one product on other products. For PCB shops focusing on a certain type of products (like rigid multilayer only,or 2 layer flex only) this optimization needs less engineering capacity per product. Prisma is designed for a manufacturer with a wide range of products (rigid,rigid-flex and flex boards) with a broad range of materials (polyimide,FR-4,LCP,molybdenum etc.) in a high-wage region (Switzerland).

Author(s)
Pascal Simon
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Results from 2007 Industry Defect Level and Test Effectiveness Studies

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To select an optimal test strategy,good knowledge of defect levels and test effectiveness are two very important factors to include. In 1999 an industry defect level study was completed and was often referred to as the “One Billion Solder Joint Study”. The content of this study was presented in several papers and articles [1],[2]. Other industry defect studies have also been done [3],[4] A study was performed in 2007 with data from 14 different companies from Asia,Europe,and Americas and with data from around 3.7 Billion solder joints inspected. This paper will present result from this updated study.
Test Effectiveness has also been presented in several papers [5],[6]. A test effectiveness study is a way to evaluate a test method’s effectiveness to detect defects and is probably the most objective way to measure these very important characteristics. This paper contains updated data from this type of study. Effectiveness from ICT (In-circuit Test),AXI (Automatic X-ray Inspection) and combined results from AOI (Automatic Optical Inspection),FT (Functional Test) and MVI (Manual Visual Inspection) will be presented.

Author(s)
Stig Oresjo
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Solder Paste Inspection Technologies: 2D-3D Correlation

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It is understood that the solder paste printing process presents far more opportunities for defects than any of the other individual Surface Mount Technology (SMT) Manufacturing Processes. In addition,transition to lead free solder paste and use of miniature components,has increased the complexity of the printing process. It has been proven that the lead free solder pastes do not spread or “wet” as well as tin lead solder pastes. In general a more accurate printing process is required in a lead free process. This has pushed the manufacturer to implement some type of post-print inspection.
The impact on the overall process must be considered when implementing in-line solutions for inspection. Factors that should be considered are,accuracy and repeatability,capability to evaluate all three Regions of Interests (ROI),cost of implementation,and speed. The three regions of interest (ROI) include the solder paste on the printed circuit board pad (both 2D and three 3D can be considered here),the region between the printed circuit board pads,and the region between the stencil apertures. Budget considerations may drive customers to consider in-line sampling techniques versus in-line 100% inspection. Sampling options today include SPI (Solder Paste Inspection) systems,both 2D or 3D,or within-printer 2D inspection.
This paper describes correlation between a true 2D area measurement (e.g. printer) and a height map generated area from a SPI system. In addition,this paper will explore the correlation between area/volume measurements and bridge detection between 2D/3D techniques. The ultimate goal is to arm the process engineers with information that can be used to make decision that will impact defects,cost,throughput and Return On Investment.

Author(s)
Rita Mohanty,Vatsal Shah,Paul Haugen,Laura Holte
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

To be or not to be (before reflow): That is the question (in AOI)

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Rarely do PCB manufacturers have the resources for purchasing an inspection machine for every stage of the manufacturing process. Typically,therefore,they have to decide whether to deploy AOI prior to the reflow oven ("in-process") or after it ("end of line"). An argument can be made for both cases. On the one hand,a high-performing post-reflow AOI machine has the capability of inspecting all fault types (solder related faults and component level faults) at the end of the line. At this point all boards can be manually fixed and some coarse level,time-delayed information can be fed back to the in-process side. On the other hand,one pays the price for finding faults at such a late stage in the process. By the time the fault has been found,multiple boards have been built - all possibly with the same faults. Thus,the in-process side of the house would suggest that AOI be moved back into the process to find faults as the boards are actually being built. Faults can be fixed immediately and process information can be fed back in a timely manner to stop faults from occurring and to prevent further faults. The theoretical economic argument is strong that earlier detection leads to reduced re-work and scrap which increases the profit margin. The in-process argument suggests that if the paste is correctly applied and the parts are correctly placed,then any solder related defects will be small if not non-existent at the end of the line. The end of line camp counters that some defects will be created by the oven and,thus,will be missed by in-process inspection. This debate of whether to deploy pre-reflow vs. post-reflow can only be settled by real empirical data. In this paper we present the results of a study at a manufacturing site in the US which contrasts using post-place inspection to find and correct defects and also to perform process control vs. using a post-reflow inspection system to find defects at the end of the line. We will quantify and contrast the benefits and drawbacks of each type of inspection alone and will also discuss any synergies between the two inspection strategies.

Author(s)
Lyle Sherwood,Pamela Lipson
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008

Fine Powder Solder Paste Applications for Semiconductor Packaging

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Fine solder powder paste applications continue to grow as a cost effective solution to many semiconductor packaging needs. Applications for solder paste continue to evolve from the standard SMT market to the semiconductor backend. This paper describes capability and process details for wafer bumping,substrate bumping,Solder on Pad,BGA ball attach and System in Package applications. For wafer bumping,quantitative bump height data,demonstrated print process,stencil design and powder size effects are discussed. For Solder on Pad,stencil design and pad finish effects are discovered. For BGA balls attach,the ability to reduce final package coplanarity is disclosed using solder paste. For System in Package,guidelines for paste printing 01005 chips are discussed. Quantitative data on material printability,dip-ability and pin transfer efficiency are covered in detail. Guidelines for suitable powder sizes for various applications are provided. Powder types from 5 through 8 are described and compared for various application processes as well as stencil and pin transfer tool designs.

Author(s)
Rick Lathrop
Resource Type
Technical Paper
Event
IPC APEX EXPO 2008