In this study,thermal cycling tests for samples of different hole-fill percentages and voiding were conducted,and cross sections of the PTH solder joints were performed to evaluate the solder microstructure,intermetallic formation,via hole-fill,and the condition of the PTH metallization and PCB dielectric prior to thermal cycling and at different times during thermal cycling. Different failure mechanisms were observed for solder joints with and without pin protrusion. PTH components with pin protrusion had better through hole-fill and less voids than PTH components without pin protrusion. The effect of hole-fill percentage and voiding on PTH solder joint reliability are discussed in detail.

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability,although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process.
This paper provides a comparison of different commonly used technologies including flip-chip,chip-size and wafer level package methodologies detailed in a new publication,IPC-7094. The IPC document describes the design and assembly challenges for implementing flip-chip technology in a direct chip attach (DCA) assembly. It considers the effect of bare die or die-size components in an uncased or minimally cased format,the impact on current component characteristics and reviews the appropriate assembly methodology. The focus of the IPC document is to provide useful and practical information to those who are mounting bare die or die size components or those who are considering flip-chip process implementation.

CSP underfill commonly acts to protect solder bumps of fine pitch CSP and enhances the reliability. This paper presents four snap curing underfills (=2min@150?or=5min@120?),tested on SnPb assemblies,to investigate on underfill processing,flux compatibility,and analyze the influence on 0.5mm pitch CSP reliability through drop and accelerated thermal cycle (ATC) test.

Choosing a Thermal Interface Material adhesive can have an impact on the reliability of the microelectronic package in harsh thermal environments where thermal cycling temperature ranges are more extreme. This can occur during assembly with lead free solders,packages that generate heat due to their small size and processing power and applications where the package is in proximity to high temperatures. Due to the differing Coefficients of Thermal Expansion and Elastic Modulus of the materials used in hybrid electronic packages,the heating and cooling causes these materials to expand and contract,creating stress on parts of assembly where failure modes can be from warping,cracking,and delamination. Epoxy TIM adhesives have been used traditionally but silicones are becoming more popular due to their inherently low elastic modulus. A simplified mathematical model was evaluated that calculates relative inherent stress based on CTE of substrate and TIM adhesive,temperature range,and Elastic modulus of TIM. The purpose was to evaluate if equation could be used to aid the engineer in a first order material selection based on desired relative inherent stress using literature values for properties above versus expensive empirical testing. Three ceramic filled TIM adhesives were evaluated; an epoxy,and two Silicones (40 Type A versus 30 „00? Durometer) using the equation and then recalculated using values from empirically obtained Elastic Modulus. The substrates considered were silicon,gold,copper and aluminum. The evaluation demonstrated that the large difference in Elastic Modulus of epoxy versus silicone did show an overall lower relative inherent stress in the package assembly.

Organic Solderability Preservative (OSP) coatings feature among the leading surface finish options in the printed circuit board (PCB) industry because of their excellent solderability,lead-free applicability,ease of processing,and low cost. OSP coatings are primarily composed of organometallic polymer with small molecules such as fatty acids and azoles entrained during the coating deposition process. OSP coatings are deposited on the Cu features of PCBs. They are transparent across the visible spectrum and they typically range in thickness from about 0.1µm – 0.6µm.
UV-Visible absorption characterization is the most frequently used technique to estimate OSP coating thickness. This method requires that a control sample be sent through the OSP line and coated with OSP. This OSP layer is then removed from the control sample using organic solvents,the solution is analyzed,and the thickness of the original coating is inferred. The OSP thickness on the active PCB is assumed to be equivalent to that of the control sample. The method is indirect,destructive,requires control samples,and does not yield any information concerning the uniformity of the coating. Furthermore,the wet-phase preparation steps make this technique susceptible to large experimental errors.
In this contribution the use of Optical Reflectivity for direct OSP metrology will be explored. Optical Reflectivity measurements are completely non-destructive,differentiating them from other technologies used to measure OSP thickness. Typically,the small probe area ensures that individual PCB features or regions of interest can be chosen for analysis. The non-destructive nature of the measurement ensures that quantitative data from OSP coatings can be collected at any time during the PCBs lifecycle. Adverse effects due to production steps and ageing on the OSP film can readily be measured. Control samples and test coupons become redundant and the circuit board itself does not require any sample preparation following OSP deposition.

Advancements and evolutions in printed circuit board manufacturing,design,and electronics assembly have driven new research on high temperature organic solderability preservative (HT OSP) surface finishes. More specifically,developments in OSP chemical processes are aimed at producing a durable finish which ensures that a board surface retains solderability through more challenging and harsh Pb-free assembly conditions. From this,it is clear that advancements in OSP processing and coating performance require a solid understanding of the mechanisms associated with coating formation and thermally driven degradation. This work examines and describes OSP structure and composition and how it is affected by heat treatments. Additionally,mechanisms of degradation of OSP are proposed along with possible strategies to remedy it.

With the increased use of lead-free alloys there has been interest in understanding the applications and limitations of final finish coatings for lead-free assembly processes. The higher temperatures needed for lead-free assembly make it more challenging to provide good protection of the underlying copper surface while maintaining acceptable solderability. Coatings that provided good solderability when using eutectic solder may no longer be acceptable when using lead-free alloys. This is especially true when multiple lead-free reflows are incorporated into the assembly process. Coatings that stand up to eutectic solder reflow temperatures may degrade or tarnish when exposed to lead-free reflow temperatures. The purpose of this paper is to provide information on the applications and limitations of OSP and immersion silver coatings in lead-free assembly processes. Solderability testing included evaluation of hole fill and wetting balance performance using SAC 305 solder. Solderability was evaluated on panels as coated as well as after durability testing. Solderability testing after multiple reflows was conducted to simulate production requirements. Surface preparation prior to application of the final finish coating was studied and included evaluation of etch type.

In general,new lead-free solder alloys with the following characteristics are desired in order to enable the continuation of miniaturization trend: (1) alloy with a reduced melting temperature,(2) alloy with a better solder spread,(3) alloy with a slower wetting speed at melting temperature,(4) a softer alloy,or alloy with a reduced voiding tendency or greater ductility,(5) alloy with a refined grain size,(6) alloy with low tendency to form large IMC plate,(7) alloy with a higher resistance toward corrosion and electrochemical migration,(8) alloy with a greater oxidation resistance. On the other hand,no-clean fluxes with the following features are needed: (1) reduced volatile,(2) halide-free,(3) greater fluxing capacity,(4) higher residue resistivity,(5) more resistant to oxidation and charring,(6) more efficient oxidation barrier,(7) lower activation temperature,(8) slower wetting speed when solder begins to melt,(9) less spattering,(10) higher probe penetratability,(11) capability of inducing nucleation of solder upon cooling,and (12) greater resistance against slump.

The change to lead-free solders has forced the electronics industry to consider more than it ever has before what properties are important in a solder. When the tin-lead eutectic was the only solder considered in most applications it was a matter of adapting products and processes to the properties of that alloy,taking advantage of its strengths and designing around its weaknesses. With what seemed like an almost unlimited range of options the electronics industry faced a dilemma when it had to choose a lead-free solder to replace the tin-lead solder that it had relied on ever since there was an electronics industry. The initial concern was melting point as it was considered essential that the replacement alloy have a melting point as close as possible to the 183°C of the tin-lead eutectic. It has since been found that higher melting point alloys can be used without a pro rata increase in process temperature. The higher yield point of most lead-free solder options seemed initially to be a bonus but it has subsequently been realised that in some circumstances compliance is more important than strength. Although some properties of tin-lead solder have turned out to be not as essential in a lead-free solder as initially expected other properties are turning out to be as important in a lead-free as they were in tin-lead. Solidification behaviour and fluidity are two examples of such properties and it has been found that lead-free solders that match tin-lead solder in that regard offer measurable performance advantages. In this paper the authors will review the solder properties they consider important in a lead-free solder and report the results of measurement of these properties in a range of lead-free solders currently used or under consideration for commercial production.

When trying to achieve 40 microns of placement spacing,bridges and tombstones may occur due to the variation of the component dimensions,equipment accuracy and pickup position variations.
Hawse have developed and patented a new process to achieve this type of spacing. This new process will be described in this paper.
Mounting components on product with 40 microns (1.6 mil) spacing is difficult due to material variations; so it is necessary to expand the spaces for mounting. By design the print deposits are shifted to the right and left of the pads. Solder paste deposits are then applied off the center of the pads. The system measures this misalignment for each deposit and feeds forward this information to the placement machine or machines to shift the placement position to match the location of the solder paste.
Controlling the position of the solder paste is very important to prevent bridges. The allowable tolerance for misalignment is about 30 microns and constantly maintaining this accuracy is extremely important. The system measures the position of the solder paste and feedbacks this information to the screen printer to maintain a constant solder paste position. Therefore it is imperative that the print position be constantly monitored. The printing condition of solder paste is controlled with the feedback feature of the system.
This system uses the properties of self-alignment of the solder paste to achieve the final result of 40 microns placement spacing. Self-alignment can be used with lead free solder paste by setting the proper reflow conditions or temperature profiles.