There has been a global trend towards legislation meant to encourage sustainable manufacturing and minimize the environmental impact of product manufacturing. In the global economy,with its distributed supply chain,local environmental laws may affect companies located anywhere in the world. Often,these laws are targeted at the finished goods manufacturer on the assumption that changes will propagate through the supply chain all the way to the raw material suppliers. Penalties for non-compliance may include monetary fines and/or trade restrictions. Compliance will likely require modifications to existing manufacturing processes,the use of alternative materials or chemicals,and new data systems to track relevant information. In order to be prepared,companies need to look ahead to identify new and future legislation and determine how it might impact their business. Companies will need to be prepared well before new legislation goes into effect. This paper takes a closer look at two upcoming European Union legislative acts that will have significant impacts on the future of electronics and semiconductor industries in Europe. Specifically,it gives an overview of the Registration,Evaluation,Authorization,and Restriction of Chemicals (REACH) regulation and Energy Using Products (EuP) Directive. REACH creates a mechanism for the registration of chemical substances manufactured or imported into the EU,a methodology for the evaluation of those chemicals and their associated safety risks,and finally establishes an authorization requirement for chemicals of high concern. Instead of concentrating on materials,the focus of EuP is on energy. EuP is part of the EU Energy Efficiency Action Plan and seeks to reduce energy usage. While these directives will affect companies within the European Union,due to global nature of modern industry,their impact will be felt far beyond the borders of the European Union.

Currently little data exists on temperature repeatability of BGA/CSP rework machine equipment. This is an issue especially for lead-free rework as the temperatures during lead-free BGA/CSP rework are likely to be higher than reflow soldering,leading to potential component and board temperature related issues. A series of evaluations was conducted on rework equipment from four rework machine equipment suppliers. The BGA/CSP rework machine repeatability and tolerance temperature study used a fixed thermal profile with temperature measurement output on equipment specifically designed for BGA/CSP rework machines. The temperature input was a lead-free rework profile developed by each supplier on a PBGA544 component on a 135mil (3.4mm) thick test vehicle board. This lead-free rework profile was run on the rework machine 10 times. Temperature peaks and durations were recorded at the 6 different temperature locations on the temperature measurement equipment placed within the rework machine.
In Phase 1 of the program each rework machine supplier recorded temperatures using its defined lead-free profile with a specific rework machine. In Phase 2,each supplier repeated these tests on a different machine of the same model. A comparison was then done to analyze the temperature and time data from Phases 1 and 2 to determine rework machine temperature repeatability and tolerances.

Wire soldering operations are still widely accepted in the electronics assembly industry. When a product or the parts within cannot withstand the heat of oven reflow,the localized heat provided by a soldering iron has been the traditional solution. In high-volume operations,this can often require large labor pools to keep up with more automated assembly processes upstream or downstream. Soldering with wire and iron also leaves process judgments up to individual operators,and can produce a wide variety of defects,scrap,or long-term quality issues.
Despite the many improvements in automated soldering technology through the years,many soldering operations are best suited to manual production methods,which produce inconsistent results. Whether in low-volume custom operations or large-scale manufacturing processes,the quality of hand-soldered joints will exhibit a high degree of variation. Defect,scrap,and rework rates can be excessive,even when using skilled employees.
Higher temperature lead-free operations present an additional challenge. Because of the higher temperatures required,these processes have even smaller operating windows. Visual inspection of lead-free solder joints also presents new difficulties,and since most hand soldering rework occurs 'on-the-fly,' actual defect rates are difficult to measure.
There are other process solutions available which involve very little capital expenditure,but can significantly increase operator output. These solutions are effective in eliminating many of the process defects associated with wire solder. They will usually result in a faster and more controllable process that reduces scrap and improves overall product quality. In many applications where wire solder was once a requirement,a more automated approach can often be achieved using solder paste and localized heating methods.

Repairing a PCB with a defective BGA,uBGA,or QFN is often a difficult and tedious task. The conventional method is to remove the defective device from the PCB; clean the pads on the PCB,then print solder paste on the pads with a mini-stencil. The stencil footprint needs to be small enough to fit into the area of the removed part,which is normally surrounded by other devices in close proximity.
This paper will describe an alternative repair method. Instead of printing solder paste on the PCB pads this system prints solder paste directly on the QFN pad or the BGA solder balls. The repair tool is simple and easy to operate. A package can be inserted in the tool,printed and placed on the PCB in about 30 seconds. The tool is made up of two components: a universal master tool,which can be reused for all packages and a unique component,which is designed for a specific package. The unique components consist of a stencil and a device holding fixture. Both are free standing metal foils with laser cut or electroformed apertures.

Over the years,the EU RoHS restriction and lead-free capability is the hottest environmental protection subject. In technology trends,signal integrity performance gets more critical based upon today’s higher signal transmission speed demand in every field of applications such as computer CPU and GPU chipset levels,system operation frequency and a variety of communication bus and cables like PCI express,SATA II and AGP bus for computer systems. Signal communication speed will shift from 1-5 Gbps range up to 5-10Gbps depending on applications. In order to meet lead-free requirements and severe processes conditions with good signal integrity performance,the laminate material will play a more and more critical and sensitive role in the system.
From consumer products to high-end applications,there is a need for certain electrical and thermal performance; it is essential to meet those requirements with cost effectiveness. As a base material supplier,we will hereby discuss material design and factors that influence signal integrity,including epoxy and hardener,resin chemical construction,laminate ply-up construction,amount of resin content,fabric weaving density,moisture pick-up and environment factors etc. for a massive mainstream application and low loss application under the hypothesis of lead-free capability.

Tombstoning,the phenomena where a chip component stands up on one end during the reflow cycle,is well-documented and understood in tin-lead systems. It is reported to occur more frequently in lead-free systems,and smaller components are at greater risk than larger ones. A comprehensive DOE was undertaken to characterize tombstoning of 0201 components in different metallurgical solder systems. Factors included pad geometry,board finish,stencil geometry,solder paste type,print and placement offsets,and reflow profile and atmosphere. The experiment was divided into two phases; the results of Phase II are analyzed and reviewed in this document.

The SMT industry is going through a challenging phase of assembling miniature components,such as micro BGA,0.3mm CSP and 01005 passives onto Printed Circuit Boards (PCB). This effort is primarily driven by the cell phone and other hand held device industries due to consumer demand for smaller devices with more functionality. Other industries,such as those that supply the defense and those in medical electronics,among others,are also expected to start using such miniature components in the near future. Because these miniature components require solder deposits that are significantly smaller per pad than other components that will reside on the same circuit board,such as QFPs,PLCC’s,there arises a challenge in SMT assembly to satisfactorily deposit solder paste for all components on the PCB.
As such,a term has arisen in the industry that has lately been used to describe this “one size fits all” process; that term is “Broadband Printing”. Broadband Printing refers to a robust printing process that provides stable process parameters that can print from the smallest to the largest pad in a single assembly with equally satisfactory results.
This paper presents the analysis from a recent printing study employing a test vehicle that includes components such as 01005s to QFPs. In a recent publication,part of this study was presented focusing on 01005 printing only. This printing process was determined to be suitable for 01005s assembly and also analyzed based on statistical capability. The current paper will present the results from additional detailed analysis to determine if this process has the capability to provide sufficient solder paste deposits for larger components located on the same test board. In the future,the SMT industry may always look towards “Broadband Printing” as an alternative to dual stencil or stepped stencil printing technologies in order to meet the needs of both small and large components.

Kitting is the first step in printed circuit board assembly. It is initiated well in advance of actual production start to be able to prepare and deliver the kit on time. Kitting involves gathering of parts needed for a particular assembly from the stockroom and issuing the kit to the manufacturing line at the right time and in the right quantity. This paper discusses kitting,describes ways to eliminate waste in different phases of kitting,and illustrates lean kitting using a case study conducted in a major contract manufacturer site.

Total cost of ownership is a financial estimate designed to help consumers and enterprise managers assess direct and indirect costs commonly related to software or hardware. It is a form of full cost accounting. However,in the world of electronics manufacturing are there any standardized,generally applicable values and guidelines that apply to the determination of the cost-of-ownership of SMT equipment,or software that manufacturers can refer to in order to make decisions that will carry them through the future?
This presentation takes a comprehensive look at the many factors to be considered when purchasing equipment such as purchase price,value retention,operating costs,output quality,ease-of-use,availability,and real performance. We will also discuss the total costs of ownership directly related to the factory flow of projects and processes and,thus,profitability. We will pay special attention to the extent to which the individual factors are truly relevant for the cost-of-ownership computation.
Based on this analysis,the presentation will cover typical COO examples in various manufacturing environments ranging from high-volume to mid-volume and low-volume environments in low-cost and high-cost countries. The presentation will introduce newly developed COO tools that let you make exact and objective COO computations in the electronics industry.
In particular,the presentation will shine light on the question to what extent placement costs have a significant impact on the overall manufacturing costs. It will also do away with some myths and assumptions around cost-of-ownership in electronics manufacturing.

Design workflow is the core to your design team?s competitive advantage; it?s the conduit by which you turn your team?s expertise and ideas into manufacturable products. And yet,all engineering teams face the challenge of maximizing their productivity within limited financial resources. How can the less-capitalized teams develop a design workflow that competes with the highly-capitalized teams? Simple: open tools.
In this session,we present business examples from both market research and from direct experience with customers and supply chain partners. From these examples,we quantify the impact of some of the key elements of a design flow based on currently available open tools:
- SDK availability
- User Interface throughput
- All free tools are the same (or are they?)
- Blurring steps in the design phase
- Moving DFM upstream for designers
And also report on areas where open distribution tools may NOT be the right choice:
- High performance signal design
- High end design