To help address the environmental requirements driven by the European Union RoHS Directive,consumer applications have changed the solder alloys for the manufacturing of printed circuit board assemblies (PCBAs) by removing Pb from solder. Based on the anticipated end to various exemptions and other market forces,high end server applications are now following suit. In addition,as the server/computer industry evolves,the requirements for speed and memory storage continue to increase,causing a need for higher levels of signal integrity along with greater density/mass of components and wiring within PCBA’s. This change to more dense/higher thermal mass components on PCBA’s and going to a Pb Free solder at higher melting temperature than SnPb Eutectic Solder will aggravate the temperature gradients that occur during reflow,causing major limitations when using standard IR/Convection reflow. Excessive temperature gradients can damage less massive components and less dense laminate areas of the PCBA’s. Consequently,other techniques need to be investigated,and the leading alternative is Vapor Phase Reflow. Vapor Phase Reflow is a legacy soldering method that was popular before the 1990's. Vapor Phase Reflow has a processing advantage: its thermal blanket possesses a much greater heat density than convection or IR heating. This reduces the temperature gradients across the board assembly,preventing sensitive components from exceeding maximum temperature limitations. One of the many concerns for implementing Pb Free Vapor Phase Reflow is the effect on solderability. The objective of this publication is to compare the solder wetting between Vapor Phase Reflow and Convection Reflow using a specific Pb Free (SnAgCu) SAC solder paste. This study will compare the amount of area the solder wetted,solder heights,wetting angles,and voiding.

It is well known that nitrogen inerting in wave soldering can significantly reduce dross formation and improve solder wetting. For lead-free wave soldering,the benefits of N2 inerting are even higher. However,there is still a lack of a mature N2 inerting technology for wave soldering,which largely impedes its wide application. This paper presents a new generation N2 inerting system for wave soldering to make the technology more cost effective and user friendly. Both lab-scale experiments and production trials were conducted,which demonstrats the following superior performances and benefits of applying the developed N2 inerting technology: 1) low N2 consumption for inerting,2) low tendency of diffuser clogging,3) low retrofitting cost,4) an option for flux vapor collection,5) reduced dross formation,6) reduced machine down time for cleaning,7) reduced flux usage,and 8) reduced soldering defects.

There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing,electroplating,or sphere dropping [1]. The choice between these technologies is highly influenced by the following criteria: the bump size & pitch requirements,cost,and overall yield. As the bumping industry evolves,many of the deficiencies and trade-offs associated with the three bumping technologies are no longer acceptable. As a consequence,a significant transition is occurring toward a fourth bumping alternative: Solder Sphere Placement [2]. This technique offers wide flexibility in bump size (40-760um),very high bump yields (>>99%) and low cost (sphere price dominated).

In PCB industry,AOI (Automated Optical Inspection) has been grown rapidly in past decades. It is now playing an important role in manufacturing process. Most manufacturers are now using AOI machines to report defects on boards after photo-printing or etching. On the other hand,AVI (Automated Vision Inspection) which sometimes also called FVI (final vision inspection) is still in early growing stage and not yet widely used in the industry.
AOI and AVI machines are both using cameras to visually find defects on PCB. But they are used in different stages of manufacturing process. AOI reports the defects on inner layers or outer layers which have only copper,base and drill holes. AVI reports the defects on final PCB products which have much more features such as solder mask,gold plate,silk screen…….
AOI and AVI machines are different kind of machines with different functions,but their working principles are very similar. Many technologies of AVI are built up from AOI. From user point of view,if there is a universal machine which can have the functions of AOI and AVI,then they may save cost,labors and space. This paper analyses on the combination of AOI and AVI to meet this objective. There are five parts in this paper. The first part focuses on the application of AOI and AVI and identifies all kinds of defects and boards which they can inspect. The second part compares the hardware and software of AOI and AVI machines. The commons and differences are found out. The third part studies of finding defects under the application and machine issues of AOI and AVI. The fourth part is to see the possibilities in combining AOI and AVI. The fifth part is to summarize the key elements that caused the Pros and Cons of the universal machine (or called combined machine).

Typical SMT production lines are a collection of disconnected machines performing various tasks. Errors can occur at any step during this process,but often go undetected until the PWB is completed and soldered and it is too late to do anything other than re-work or scrap it. New tools with better integration are required to support the demand for increased yields and improved efficiency.
To prevent defects from simply passing from one machine on to the next,it is necessary to have inspections throughout the line. Better yet,sensing at different points should be linked to form a complete solution. This is especially critical in the placement phase of assembly due to the wide variety of inputs (components) and movements. The assembly system has to take up to hundreds of different components and individually place them at different locations on the PCB. This complicated task requires more thorough oversight to ensure defects are not created or passed on. Optical sensors can provide this oversight into the assembly process and offer the benefits of being fast,accurate,and non-contact.
Some of the challenges of integrating these sensing technologies are cost and space. It would be too expensive to have a complete inspection machine before and after each assembly system and take up far too much space. New generations of optical sensors,however,are also compact enough such that they can be embedded at key locations within the PCB assembly process. These sensors can be integrated to form a complete web of error prevention.
This paper discusses the new integrated optical sensing technologies that make it possible to virtually guarantee that only good PCBs will pass through the assembly process,reducing costly rework or scrapped PCBs and improving efficiency.

A PCB fails final test. Why? Was it the solder paste? The screen printer? The PCB assembly machine? The reflow oven or none of the above?
Unplanned downtime is a costly fact of life. In order to minimize the length of downtime it is necessary to have clear details on exactly what the source of the problem is,not just the symptoms. This information allows operators and maintenance personnel to go directly to take corrective steps more quickly and minimize downtime.
There are many machines and materials involved in the assembly of a complete PCB; screen printers,conveyors,pick and place systems,reflow ovens,Automated Optical Inspection (AOI),solder paste and components. Some of this equipment has the ability to check its results before,during or immediately after it has completed its task.
Until now there have been few real-time tools for the pick and place systems. In many cases,high speed movement on these machines makes it extremely hard to “see” exactly what is happening. Components misplaced by the assembly system could be caused by many different factors. Without tools to provide a clear view of very high speed placement,it is difficult to the cause of misplacement.
How much easier would this task be if operators and maintenance personnel are armed with detailed information on the nozzles,feeders,and actual images of the picking and placing of parts on the PCB?
This paper will discuss tools available for the placement machine to assist in root cause failure analysis (RCFA).

3D is the shorthand term for the three dimensions of Cartesian coordinate space X,Y and Z. With that definition in mind,one will find with little or no stretching of the imagination,that the first electrical interconnections,performed using discrete wires were unquestionably 3D. If one doubts it they can look at almost any electrical product from the time of the 19th century telegraph onward. 3D interconnections are found virtually everywhere. It is really 2D that is more illusive if one thinks about it. Even so,3D interconnection solutions and options have dominated the electronics manufacturing industry's attention over the last few years and interest in the topic has been accelerating. The reasons for this interest are manifold but the root cause is that the third dimension provides the ability to extend the pursuit of ever greater density when the acknowledged physics based limits that will ultimately spell the end of Moore's Law kick in. In order to keep delivering the promise of better cost/performance metrics for each new generation of electronics,interconnection technologies which take advantage of the third dimension will play an increasing important role in the future. In fact electronic interconnection
technologies will undoubtedly pace price and performance improvements for most if not all future electronic products and 3D
interconnections will play a pivotal role. This paper discusses 3D solutions which have been used from past to present from chip to system and will included a glimpse of what might be ahead.

After the implementation of RoHS and the discontinued use of lead bearing products and the introduction of lead free (LF)
solders,tin and its alloys have come to the forefront as the first choice of replacement to tin-lead.
On the solder side the transition has moved forward and solutions have been implemented,like the SAC family of LF solders
for paste reflow and tin-copper for HASL (hot air solder leveling). The industry is constantly making progress adapting its
materials and processes to the higher reflow temperature profile for these LF solders. Today there is a much better
understanding of the types of solder joints that are formed; their reliability and the type of intermetallic compound (IMC)
formed.
On the surface finish side,replacing tin-lead has posed greater challenges. Component leads and connector finishes were
being converted to tin as an obvious alternative. This works well as a soldering surface,however any part of the lead or the
connection surface that is not soldered to,has shown a potential to form tin whiskers over the life of the part. Internal stresses
in the deposit due to IMC formation or external stresses on the deposit are known to initiate whisker formation.
In this paper two approaches are implemented to dissipate the stress that is formed,the first is to modify the substrate surface
to control the growth in thickness and direction of propagation of the IMC and the second is to modify the large columnar tin
deposit crystal structure to mimic the fine equiaxed structure of tin-lead solder. The former is achieved thru controlled micro
roughening of the substrate and the latter by the use of additives to the plating bath.
Data will be presented to show the effect of each of the two approaches on the dissipation of the stress,resulting from IMC
formation. As the stress is dissipated the primary cause of whisker formation is eliminated.

In recent years the PCB industry has increasingly turned to digital,or maskless,imaging techniques in order meet demands for tighter registration between layers. Many of these techniques,including laser direct imaging (LDI),rely on a “dot-matrix” style exposure technique that uses “binary” pixels and small pixel or dot spacing to achieve the required resolution. This results in limitations in write speed and throughput,since many small pixels or dots must be written over a relatively large area PCB substrate. A patented gray level technique1 based on a commercially available digital micro-mirror device (DMD) achieves required resolutions with a relatively large projected pixel size,and thus offers a higher speed alternative to conventional digital techniques. Gray level,or dose control as a function of panel position can also provide some degree of compensation for minor processing or development artifacts that are known to recur in the same areas of a panel.

•Background and Objective
•Head-in-Pillow (HiP) Defect
•In Circuit Test (ICT) Testability
•Evaluation Steps
- Solder Paste Selection
- Head-in-Pillow Test
- Printability & Solderability Tests
- Surface Insulation Resistance (SIR),Electrochemical Migration (ECM) & Ion Chromatography (IC) Tests
- Verification Build