This paper details the Alcatel-Lucent Pb-free Material Reliability Test board (MRT) used in two different High Density Packaging User Group tests covering 56 different constructions and in numerous other independent material analysis studies [1-7]. In total,this test vehicle has been used in over 80 different material evaluations (and still growing) encompassing materials from almost every major material manufacturer and fabricated by multiple PWB manufacturers. The test vehicle,currently in its 5th generation (MRT-5),is very comprehensive and includes sections for evaluation of material survivability through Pb-free reflow at different via hole pitches,air-to-air thermal cycling,interconnect stress testing (IST) – including the new DELAM methodology introduced by PWB Interconnect Solutions [5,9],conductive anodic filament (CAF) evaluation,moisture sensitivity and its effect on Pb-free reflow survivability,electrical characterization,provides BGA pads for pad pull testing,and incorporates specific design features to enable characterization of material properties (such as DMA) in a multilayer construction in a consistent manner. The design is flexible including 3 different standard constructions and resin contents (12 layer,and 20 layer with 2 different constructions) and can be adapted to other configurations if necessary. This paper presents the design and provides example results and information on how to evaluate these results. The design is made available to all in the industry to facilitate a standard test methodology – and has been offered to IPC as a standard test vehicle for multilayer material evaluations.

The High Density Packaging Users Group Consortium investigated plated through hole reliability of printed wiring board test vehicles constructed with 20 different Pb-free capable printed wiring board materials. The study contained a total of 27 different constructions built by three PWB manufacturers. The materials were tested using both air-to-air thermal cycling and Interconnect Stress Testing (IST) methodologies. The test vehicles combined both via reliability and materials analysis testing capabilities,using two specially designed IST coupons with via to via spacing of both 0.040” (1mm) and 0.032” (0.8mm),All products were constructed with 20 layers,laminated to an average thickness of 0.115” (2.92mm),and drilled with 0.010” (0.254mm) vias,producing an aspect ratio of 11.5 to 1. Seven of the 20 materials were investigated with two different glass styles and resin contents. The materials were IST tested on the two coupons types,both as built and after 6X Pb-free (260°C) reflow. The air-to-air thermal cycling tested a single configuration after 6X Pb-free reflow only. Materials in the test included eight high Tg,filled FR4 materials,six high Tg halogen-free FR4 materials,and six high speed materials. Correlations between the air-to-air thermal cycling results and IST results are detailed,as are the correlations of these results to independently measured and supplier listed material properties.

An important element of the High Density Packaging Users Group (HDPUG) Consortium investigation into the reliability of printed wiring board (PWB) constructed with 20 different Pb-free materials was to understand whether the materials were negatively impacted by the six reflow cycles to 260°C. A new electrical test methodology and associated automated test equipment have been developed to non-destructively measure and compare specific attributes of the PWB’s material construction that identify whether material degradation (delamination) was present. Additional features of the methodology create product construction baselines which confirm that each individual test vehicle was constructed with the same material properties,thickness and glass/resin ratio,all related to changes in dielectric material properties. The data enables the user to estimate the variability of thickness for each dielectric layer within the product construction. The study contained a total of 27 different constructions; built by three high-end Asia based PWB manufacturers. The Interconnect Stress Test (IST) test vehicles were designed to combine attributes to quantify both via reliability and materials analysis testing. Via reliability results and the statistical correlation between IST and air to air oven testing is reported in a separate paper [5]. Using two specifically designed IST coupons with via-to-via spacing of both 0.040” (1mm) and 0.032” (0.8mm),all products were constructed with 20 layers,laminated to an average of 0.115” (2.92mm),drilled with a 0.010” (0.254mm) vias,producing an aspect ratio of 12 to 1. Seven of the 20 materials were manufactured with two different glass styles and resin contents. The materials were tested on the two coupons types,both as built (non-stressed) and after 6X Pb-free (260°C) reflow (stressed). Twenty different material types were tested,which included eight high Tg,filled FR4 materials,six high Tg halogen-free FR4 materials,and six high speed materials. Correlations between the electrical testing and traditional micro sections for the presence of material damage and confirmation of dielectric thickness are detailed.

Accelerated testing of plated hole life is necessary for economic reasons due to the long time to failure during field operating conditions. One difficulty in performing accelerated testing on plated holes is to decide which acceleration model to use. In the work presented here,we will assume an inverse power law relation of cycles to failure versus stress. Stress versus temperature curves will be derived from TMA and DMA data from over twenty lead-free laminates,before and after reflow thermal stress. We will then compare stress versus cycle to failure data for both the lead-free laminates and the two thermal stress conditions,ATC and IST. Completion of this work will enable prediction of plated hole cycles to failure based upon laminate material properties and help to better understand the key role that laminate materials play in plated hole reliability. Also,the two stress conditions will be compared with respect to field life predictions

- COMPONENTS
- Risk Mitigation Testing Strategies Examples
- Risk Mitigation Testing Affiliations
- IDEA – 1010
- AS5553
- Mil-Std-1580

Counterfeiting is a widespread problem that affects every industry and which has the potential to significantly erode a company’s bottom line. According to the International Anti-Counterfeiting Coalition (IACC),the global trade in counterfeit products has increased from $5.5 billion in 1982 to approximately $600 billion annually today. In the U.S. alone,counterfeit goods cost businesses between $200 billion to $250 billion annually [1].
The impact of counterfeit products is not just about tangible financial losses. Counterfeit products can negatively impact a company’s brand,reputation and perceived commitment to quality. Because counterfeit products can also expose consumers to potential safety hazards,their availability may carry legal ramifications for companies.
The good news is that companies can assess the risk of being targeted by counterfeiters,and can implement a plan to protect against such risks. By following the appropriate steps,companies can determine how to protect their physical and intellectual property assets,identify the elements of an anti-counterfeiting program and implement an anti-counterfeiting plan. However,any anti-counterfeiting plan must be tailored to a specific company’s needs,based on size of the company,the type of products,the complexity of the supply chain and the markets in which the company does business.
Many companies have taken rigorous steps to protect their intellectual property,the quality of their products and their reputation in the marketplace. These steps include the introduction of holographic labels,the use of special color schemes to identify specific product types and the application of overt and covert security coding. In addition,a number of companies have partnered with customs officials in anti-counterfeiting efforts,resulting in the seizure of millions of counterfeit products,including electronic products.

DNA is a form of forensic evidence trusted by law enforcement and recognized by international courts around the world. This abstract provides an introduction to the utility of botanical DNA taggants to safeguard electronic components in supply chains and to protect against counterfeiting and diversion. A detailed treatment of the science behind Applied DNA Science’s botanical DNA technology,its applications to semiconductors and microchips and an overview of DNA analysis by PCR and CE analysis is provided.

Counterfeit electronic parts have become a significant cause of worry in the electronics part supply chain. Most of the counterfeit parts detected in the electronics industry are either new or surplus parts or salvaged scrap parts. The packaging of these parts is altered to modify their identity or to disguise the effects of salvaging. The modification can be as simple as the removal of old marking and then adding new marking,or as complicated as recovery of a die and repackaging.
In this chapter,we discuss the type of parts used to create counterfeits and the defects/degradations inherent in these parts due to the nature of the sources they come from,proposed inspection standards,and limitations of these standards. The processes used to modify the packaging of these parts to create counterfeits are then discussed along with the traces left behind from each of the processes. We then present a systematic methodology for detecting signs of possible part modifications to determine the risk of a part or part lot being counterfeit.

Several U.S. Government (USG) regulations require parties engaged in import activities to maintain records of transaction processes. By using formal documented tools integrating these regulations within existing quality management systems,organizations can mitigate risk throughout their supply chain and simultaneously comply with AS5553.

For the electronics on PCB’s,dielectric materials provide not only material and media support for the high-speed digital and RF systems,but also electrical performance. Impedance control and signal integrity have become increasingly important in high frequency applications,while trends in electronic industry continue to drive high-speed digital,RF and microwave systems for high-density integration,high system performance and high power operations over a wide range of operating temperatures. Microstrip and stripline are widely used in the high data rate and high frequency circuitry designs because they can be easily and cost-effectively fabricated with high performance,planar PCB laminates for various applications. To obtain optimal signal/power transmission,signal integrity and low signal distortion,certain controlled impedance (typically 50O) is very important to minimize impedance mismatching and power reflection. In practical designs,characteristic impedance of transmission lines is a complex function of substrate dielectric properties and physical structures,such as dielectric constant (er),trace width (W) and substrate thickness (h or b),or even metal strip thickness (t). However,when designers come to selecting the proper PCB laminates for their designs,there is lack of design tools for them to quantitatively evaluate the target board materials in terms of impedance control to effectively compare their temperature performance in terms of key PCB material properties,such as dielectric constant thermal stability and substrate thermal expansion. In this paper,based on the practical design equations for microstrip and stripline circuitry and using the Taylor series expansion (e.g. ?Z=dZ/dk*?k+dZ/dW*?W+dZ/dh*?h+dZ/dt*?t) for linear approximation of multiple-variable functions (e.g. Z0=Z(k,W,h,t)),analytic design equations for evaluating the transmission line impedance variations from its board dielectric and dimensional change have been developed. Additionally,these analytic design tools can also be readily applied to evaluate the variations of planar transmission lines for practical design and PCB fabrication impedance control with the board material’s dielectric constant and dimensional stability resulting from substrate tolerances (i.e. laminate DK and thickness tolerance) and PCB processing (such as trace etching resolution,multilayer thickness and etc.).