Functional Test on RF And High-Speed Connectors on PCBA's And Cable Harness Assemblies for Automotive Applications

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This paper presents test methods to effectively perform conducted testing on RF and high-speed data connectors for automotive applications. In almost any modern vehicle there are numerous high frequency and high-speed connectors which are used for applications such as cameras, internet connectivity thru cellular data, safety tasks, car entertainment, etc. These connectors are not easy to test. For example, a cable harness connector may have a hermetical seal which makes it hard to contact with a test probe. Connectors on printed circuit board assemblies and modules may be very small and densely spaced, which leads to additional testing challenges. This paper presents how typical RF and high-speed connectors from the automotive industry look like, describe the difference between single-ended and multi-signal / high speed connectors and show spring-loaded test pins that are used to establish temporary electrical contact for the purpose of electrical test. Electrical tests include tests that are done "at speed" as well as simpler applications such as continuity checks. Hi pot testing on such connectors and what that means for the test probe are also addressed. Furthermore, there is a deep dive into test fixture topics and a demonstration of why flexible cabling is a must and how to route wiring for such tasks inside a shielded or unshielded test apparatus. Such fixtures typically are also densely packed - there's not a lot of room for cabling - yet at the same time a simple mistake can cause test probes to be misaligned or worse to get damaged beyond the possibility of repair and there is a demonstration on how to prevent that. After this talk, engineers will have what it takes to successfully plan a test strategy to do functional testing for such applications.

Author(s)
Matthias Zapatka
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

Rapid Assessment of Solder Resist-Related Electrochemical Reliability Issues

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In comprehensive humidity tests for the release of materials and processes for the assembly and interconnect technology of PCBAs of the automotive industry, the solder resist has emerged as a particular focus of defects with regard to electrochemical migration. Anodic migration phenomena inside the solder resist in high voltage applications or even insufficient hydrolysis resistance at GND lines with electrochemical migration through the solder resist are recurring failure patterns. Typical SIR tests, even when extended to 504h, have insufficient sensitivity to these failure patterns. Neither suspected material influences nor differences between process variants in solder resist application or between PCB manufacturers could be clearly detected with standard SIR tests.

With this in mind, a solder resist stress test (SRS-test) was developed to provide a simple means of detecting the isolation effect of solder resist as required by IPC-SM-840 [1]. It is based on the use of the IPC-B53 (IEC TB144) test board [6], where the test structures have been alternately covered by solder resist. Each GND line thus represents an isolator. The test is now accelerated by partially immersing the B53-test PCB in a water bath and applying a voltage. The electric current flow in the test medium is now recorded as a function of time. A failure of the insulation effect is detected by a sudden increase in the measuring current, which occurs within 3h to 300h depending on the solder resist material and processing. A good sensitive resolution between different solder resist materials and processes at the PCB supplier was thus achieved, as well as a reduction of test times compared to standard SIR test. A classification of the solder resist quality into resistance classes is possible by this procedure.

With this method, dependencies on the test voltage, the test temperature, different types of solder resist, but also their application processes were worked out. A tool was established with which solder resist suppliers and PCB manufacturers can optimize their formulations and application processes for the automotive industry without having to publish the usually sensitive data on the formulation and processes. In addition, the tool offers the possibility to detect deviations from the required resistance class (SRS class) by means of a recurring qualification. This simple test closes the currently existing comprehensive specification gap with regard to solder resist quality in terms of insulation effect.

Author(s)
Lothar Henneken
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

IPC Advanced Packaging Symposium: Building the IC-Substrate and Package Assembly Ecosystem

Date
-

Inviting you to the IPC Advanced Packaging Symposium: Building the IC-Substrate and Package Assembly Ecosystem to be held at the Kimpton Hotel Monaco in Washington D.C., October 11-12, 2022.

AGENDAREGISTRATION OPTIONS | MEET THE SPEAKERSSPONSORSHIPS | HOTEL

The electronics industry is in the early stages of a new era, with unprecedented change already in motion. In this era of ‘Heterogeneous Integration’ led by massive changes in semiconductor and advanced packaging sectors, the days of following Moore’s Law are over! Chiplet-based design architectures incorporating heterogeneous integration packaging methods will enable next-generation electronic systems and applications. These fundamental changes in the semiconductor sector have significant impact throughout the rest of the electronics supply chain. As lines blur between IC-Substrate and HDI printed circuit board technologies and capabilities, the lines between OSAT and EMS manufactures also blur. Please join us for this important symposium focused on IC-Substrates and OSAT manufacturing.

This symposium has been designed for executives, government, and industry leaders to meet in-person and share insights. The discussion will move past the hype to identify key business and technology issues with near- and longer-term solutions. Focused on opportunities and challenges for next-generation advanced packaging production, the top-down agenda will cover public policy updates, commercial and defense electronics technology drivers, current business environment for IC-Substrates and component assembly & test manufacturing.

This 2-day event is dedicated to in-depth discussions on strengthening the IC-Substrate and Package Assembly Ecosystem in North America and Europe. The intent of the symposium is to bring Commercial and Defense Electronic Industry leaders together to:

  • focus on highest priority needs for IC-Substrates and Advanced Packaging spanning the next 3-10 years,
  • identify key challenges to overcome that enable sustainable businesses over the long run,
  • move beyond general issue awareness and focus on ‘punching through’ into actionable research, development, design, materials, manufacturing, and business operations execution needs/projects, and
  • enable attendees to walk away with actionable next steps and an expanded network for continued development efforts. 

Speakers will span the advanced packaging ecosystem and semiconductor supply chain: component makers, HDI PCB fabricators, market leading IC-Substrate fabricators, assembly & test manufacturers, equipment, and material suppliers. Four featured keynote presentations will include senior leaders at Intel, US Department of Defense, SRC Semiconductor Research Corporation, and TechSearch International. With 28 speakers and 8 sessions, the agenda will also include the latest insights from speakers representing the US Department of Commerce, the European Commission, Intel, National Institute of Standards and Technology (NIST), Northrop Grumman, Raytheon, Schweizer Electronic, SEMCO, SkyWater, TTM, Western Digital, and others. 

EVENT SPONSORS

Advanced Packaging Sponsors
Gray Line
Remote video URL

“Everything follows silicon.” Matt Kelly, IPC chief technologist, participates in the Reliability Matters podcast with host Mike Konrad, covering issues from restoring North American competitiveness and what factors led to its lag in tech, to the opportunities expected from the passage of the CHIPS+ Act, and detailed information on IPC’s upcoming advanced packaging symposium.

Nolan Johnson from I-Connect speaks with IPC’s Chris Mitchell, vice president of global government relations, and Matt Kelly, chief technologist, about the inaugural IPC Advanced Packaging Symposium. In this conversation, Mitchell and Kelly detail the symposium's objectives, presenters, and the the attendance value to both fabricators and assemblers in attending. 

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Gray Line

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IPC has undertaken a thorough, data-driven analysis of the global semiconductor and advanced packaging ecosystem and makes recommendations to address capability and capacity gaps within North America. This study is intended to help inform government policy and investment strategy to strengthen the North American advanced packaging ecosystem.

AGENDA

The agenda includes confirmed speakers from: 

  • AGC Taconic
  • AMD
  • Amkor Technology, Inc.
  • AT&S
  • Averatek Corporation
  • Calumet
  • U.S. Department of Commerce
  • U.S. Department of Defense
  • GreenSource Fabrication
  • IBM Research
  • Integra Technologies
  • Intel Corporation
  • Lam Research
  • NIST
  • Northrop Grumman
  • OKUNO
  • Samsung Electro-Mechanics Pte.,Ltd. (SEMCO)
  • Sanmina
  • Semiconductor Research Corporation (SRC)
  • Schweizer Electronic
  • SkyWater
  • TechSearch Intl.
  • TTM Technologies
  • Western Digital

7:00 am – 8:00 am | Networking Breakfast

8:00 am – 8:15 am | Welcome Remarks and Introductions
Opening Remarks
John W. Mitchell
President and CEO
IPC

Matt Kelly, P.Eng., M.B.A.
Chief Technologist
IPC

8:15 am – 9:00 am | Setting the Stage: Building the North American Advanced Packaging Ecosystem:  Economic Challenges and Opportunities
Jan Vardaman
Founder and President
TechSearch International Inc.

9:00 am – 9:45 am | Supporting Moore’s Law with Advanced Packaging
Tom Rucker, Ph.D.
Vice President Technology and Development
Intel Corporation

9:45 am – 10:10 am | Break

10:00 am – 10:45 am | Defense Perspectives Keynote: DoD Microelectronics Strategy
Devanand Shenoy, PhD
Principal Director for Microelectronics
Director, Defense Microelectronics Cross-Functional Team
Office of the Under Secretary of Defense for Research and Engineering
Office of the Deputy Chief Technology Officer for Critical Technology

10:45 am – 11:30 am | U.S. CHIPS Act Implementation   
Moderator, Chris Mitchell 
Vice President Government Relations, IPC

NIST, Semiconductors, and the CHIPS & Science Act
Frank Gayle, ScD 
Deputy Director
NIST Office of Advanced Manufacturing & Advanced Manufacturing National Program Office

11:30 am – 12:00 pm | Advancing a European Chips Act
Moderator, Chris Mitchell
Vice President Government Relations, IPC

A Chips Act for Europe
Francisco J. Ibáñez
Senior Expert, Microelectronics and Photonics Industry
DG CONNECT
European Commission

12:00 pm – 1:00pm | Lunch

1:00 pm – 2:30 pm | Component OEM  - Commercial Perspectives, Needs, and Challenges

Emerging Microelectronic Technologies for Radiation Hardened Applications
Thomas Boone, Ph.D.
Senior Technologist, Defense and Aerospace Research
Western Digital 

First level Packaging and Supply Chain Considerations for HPC: A System Perspective
Dale McHerron, Ph.D.
Senior Manager, Heterogeneous Integration Research
IBM Research, AI Hardware Center

Advanced Packaging – Future of Technology & Supply Chain
Deepak Kulkarni, Ph.D.
Fellow, Advanced Packaging Substrate Technology Development
AMD

2:30 pm – 2:45 pm | Break

2:45 pm – 4:15 pm | North American Defense Needs and Perspectives
Addressing DoD Advanced Packaging Needs
Darren Crum, PhD
Advanced Packaging Lead & SHIP Digital Technical Manager
Office of the Under Secretary of Defense for Research and Engineering

Establishing Domestic Advanced Packaging Capability for DoD Applications
Helen Phillips
Director, Advanced Operations Northrop Grumman Mission Systems
Northrop Grumman 

Advanced Packages for Modernization of Defense Systems
Kim Eilert
Technology Development Manager in Advanced Electronics
FAST Labs BAE Systems

4:15 pm – 4:30 pm | Day 1 Wrap-up 

5:00 pm – 6:30 pm | Networking Reception

7:00 am – 7:45 am | Networking Breakfast

7:45 am – 8:00 am | Welcome Remarks
Matt Kelly, P.Eng., M.B.A.
Chief Technologist
IPC

8:00 am – 8:45 am | SRC Keynote – Packaging is the New King
Todd Younkin, Ph.D.
President and CEO
Semiconductor Research Corporation (SRC)

8:45 am – 10:15 am | Importance of IC-Substrates – Advanced Package Assembly Perspectives

Future Trends for Chiplet Heterogeneous Integrated Packaging (CHIP)
Charles Woychik, Ph.D.
Senior Director, Advanced Packaging Platforms
SkyWater Technology 

From Global to Local: The Journey to Supply Chain Localization
Kevin Engel
Corporate Vice President, Flipchip / Wafer Level Business Unit
Amkor Technology, Inc. 

Trends in SIP and Highspeed Substrates
Matt Bergeron 
VP Business Development 
Integra Technologies 

10:15 am – 10:30 am | Break

10:30 am – 12:00 pm | Panel Discussion – North American Perspectives on the IC-Substrate Market 
Moderator: Matt Kelly, P.Eng, MBA 
Chief Technologist
IPC 

General Principles for a North American Package Substrate Industry
Haris Basit
Chief Executive Officer
Averatek Corporation

Adopting New Process Technology to an Old Problem
Meredith LaBeau, Ph.D.
Chief Technology Officer
Calumet  

The Necessity of Process Synergies
Michael Gleason
Director of Product Development
GreenSource Fabrication LLC

The Foundational Requirements for High Impact Substrate Manufacturing
Jim Fuller
Vice President, Engineering and Technology Development
Sanmina 

Barriers and Opportunities in Advanced Packaging Ecosystem
Matt Neely 
Director of Process Engineering, North America 
TTM Technologies

12:00 pm – 1:00 pm | Lunch

1:00 pm – 2:30 pm | Global Perspectives on IC-Substrate Market

Yesterday, Today, and Tomorrow on Package Substrate Industry
Richard (KwangWook) Bae 
Executive Vice President of NPI, CTO 
Samsung Electro-Mechanics Pte.,Ltd. (SEMCO)

Advanced Substrates & Packages are Crucial – How Can the U.S. Achieve its Sovereignty?
Mario Ibrahim
Business Development Manager
and
Walter Moser
Director Public Affairs Global
AT&S

IC Substrates for Power Packaging - Technologies and Supply Chain Aspects
Thomas Gottwald
Vice President Technology
Schweizer Electronic 

2:30 pm – 2:45 pm | Break

2:45 pm – 4:15 pm | IC-Substrate Material and Equipment Advancements

Idealism vs Realism – Bulletproof Stacked Microvias Built with Common Sense, Good Engineering, the Proper Material
Tom McCarthy
Vice President of Innovation 
AGC Taconic 

Electroless Copper Plating Process "OPC FLET process" with Excellent Via Connection Reliability
Naoki Okuno
Chief Administrative Officer
OKUNO

Equipment Challenges for Panel Level Packaging 
John Ostrowski
Managing Director, SABRE 3D
Lam Research

4:15 pm – 5:15 pm | Final Session – So What’s Next?
More information coming soon

5:15 pm | Symposium Concludes 

7:00 am – 8:00 am | Networking Breakfast

8:00 am – 8:15 am | Welcome Remarks and Introductions
Opening Remarks
John W. Mitchell
President and CEO
IPC

Matt Kelly, P.Eng., M.B.A.
Chief Technologist
IPC

8:15 am – 9:00 am | Setting the Stage: Building the North American Advanced Packaging Ecosystem:  Economic Challenges and Opportunities
Jan Vardaman
Founder and President
TechSearch International Inc.

9:00 am – 9:45 am | Supporting Moore’s Law with Advanced Packaging
Tom Rucker, Ph.D.
Vice President Technology and Development
Intel Corporation

9:45 am – 10:10 am | Break

10:00 am – 10:45 am | Defense Perspectives Keynote: DoD Microelectronics Strategy
Devanand Shenoy, PhD
Principal Director for Microelectronics
Director, Defense Microelectronics Cross-Functional Team
Office of the Under Secretary of Defense for Research and Engineering
Office of the Deputy Chief Technology Officer for Critical Technology

10:45 am – 11:30 am | U.S. CHIPS Act Implementation   
Moderator, Chris Mitchell 
Vice President Government Relations, IPC

NIST, Semiconductors, and the CHIPS & Science Act
Frank Gayle, ScD 
Deputy Director
NIST Office of Advanced Manufacturing & Advanced Manufacturing National Program Office

11:30 am – 12:00 pm | Advancing a European Chips Act
Moderator, Chris Mitchell
Vice President Government Relations, IPC

A Chips Act for Europe
Francisco J. Ibáñez
Senior Expert, Microelectronics and Photonics Industry
DG CONNECT
European Commission

12:00 pm – 1:00pm | Lunch

1:00 pm – 2:30 pm | Component OEM  - Commercial Perspectives, Needs, and Challenges

Emerging Microelectronic Technologies for Radiation Hardened Applications
Thomas Boone, Ph.D.
Senior Technologist, Defense and Aerospace Research
Western Digital 

First level Packaging and Supply Chain Considerations for HPC: A System Perspective
Dale McHerron, Ph.D.
Senior Manager, Heterogeneous Integration Research
IBM Research, AI Hardware Center

Advanced Packaging – Future of Technology & Supply Chain
Deepak Kulkarni, Ph.D.
Fellow, Advanced Packaging Substrate Technology Development
AMD

2:30 pm – 2:45 pm | Break

2:45 pm – 4:15 pm | North American Defense Needs and Perspectives
Addressing DoD Advanced Packaging Needs
Darren Crum, PhD
Advanced Packaging Lead & SHIP Digital Technical Manager
Office of the Under Secretary of Defense for Research and Engineering

Establishing Domestic Advanced Packaging Capability for DoD Applications
Helen Phillips
Director, Advanced Operations Northrop Grumman Mission Systems
Northrop Grumman 

Advanced Packages for Modernization of Defense Systems
Kim Eilert
Technology Development Manager in Advanced Electronics
FAST Labs BAE Systems

4:15 pm – 4:30 pm | Day 1 Wrap-up 

5:00 pm – 6:30 pm | Networking Reception

7:00 am – 7:45 am | Networking Breakfast

7:45 am – 8:00 am | Welcome Remarks
Matt Kelly, P.Eng., M.B.A.
Chief Technologist
IPC

8:00 am – 8:45 am | SRC Keynote – Packaging is the New King
Todd Younkin, Ph.D.
President and CEO
Semiconductor Research Corporation (SRC)

8:45 am – 10:15 am | Importance of IC-Substrates – Advanced Package Assembly Perspectives

Future Trends for Chiplet Heterogeneous Integrated Packaging (CHIP)
Charles Woychik, Ph.D.
Senior Director, Advanced Packaging Platforms
SkyWater Technology 

From Global to Local: The Journey to Supply Chain Localization
Kevin Engel
Corporate Vice President, Flipchip / Wafer Level Business Unit
Amkor Technology, Inc. 

Trends in SIP and Highspeed Substrates
Matt Bergeron 
VP Business Development 
Integra Technologies 

10:15 am – 10:30 am | Break

10:30 am – 12:00 pm | Panel Discussion – North American Perspectives on the IC-Substrate Market 
Moderator: Matt Kelly, P.Eng, MBA 
Chief Technologist
IPC 

General Principles for a North American Package Substrate Industry
Haris Basit
Chief Executive Officer
Averatek Corporation

Adopting New Process Technology to an Old Problem
Meredith LaBeau, Ph.D.
Chief Technology Officer
Calumet  

The Necessity of Process Synergies
Michael Gleason
Director of Product Development
GreenSource Fabrication LLC

The Foundational Requirements for High Impact Substrate Manufacturing
Jim Fuller
Vice President, Engineering and Technology Development
Sanmina 

Barriers and Opportunities in Advanced Packaging Ecosystem
Matt Neely 
Director of Process Engineering, North America 
TTM Technologies

12:00 pm – 1:00 pm | Lunch

1:00 pm – 2:30 pm | Global Perspectives on IC-Substrate Market

Yesterday, Today, and Tomorrow on Package Substrate Industry
Richard (KwangWook) Bae 
Executive Vice President of NPI, CTO 
Samsung Electro-Mechanics Pte.,Ltd. (SEMCO)

Advanced Substrates & Packages are Crucial – How Can the U.S. Achieve its Sovereignty?
Mario Ibrahim
Business Development Manager
and
Walter Moser
Director Public Affairs Global
AT&S

IC Substrates for Power Packaging - Technologies and Supply Chain Aspects
Thomas Gottwald
Vice President Technology
Schweizer Electronic 

2:30 pm – 2:45 pm | Break

2:45 pm – 4:15 pm | IC-Substrate Material and Equipment Advancements

Idealism vs Realism – Bulletproof Stacked Microvias Built with Common Sense, Good Engineering, the Proper Material
Tom McCarthy
Vice President of Innovation 
AGC Taconic 

Electroless Copper Plating Process "OPC FLET process" with Excellent Via Connection Reliability
Naoki Okuno
Chief Administrative Officer
OKUNO

Equipment Challenges for Panel Level Packaging 
John Ostrowski
Managing Director, SABRE 3D
Lam Research

4:15 pm – 5:15 pm | Final Session – So What’s Next?
More information coming soon

5:15 pm | Symposium Concludes 

MEET THE SPEAKERS

Richard (KwangWook) Bae

Richard (KwangWook) Bae
Samsung Electro-Mechanics Pte.,Ltd. (SEMCO) 

Bio

Executive Vice President of NPI, CTO 

Mr. Richard (KwangWook) Bae is a Chief Technology Officer and a leader on the NPI (New Product Introduction) and the technical Sales at Strategic Marketing Center, Samsung Electro Mechanics. 

He had been a Chief Strategy Officer for 7 years and a Head of Samsung Electro Mechanics US Lab for 5 years. 

He led Samsung’s Fan Out PLP (Panel Level Package) business 5 years ago and now he is leading 2.nD package business of Samsung Electro Mechanics. 

Darren Crum

Darren Crum, Ph.D.
Office of the Under Secretary of Defense for Research and Engineering

Bio

Advanced Packaging Lead & SHIP Digital Technical Manager

Dr. Darren Crum is a technical leader with more than 20 years of experience in advancing microelectronics engineering in the defense industry. He is a Technical Area Lead and Program Technical Manager for microelectronics advanced packaging at the Naval Surface Warfare Center, Crane Division directly supporting the Office of Under Secretary of Defense for Research & Engineering’s Trusted & Assured Microelectronics Program and the SOTA Heterogeneous Integrated Packaging (SHIP) Program. He also serves as a government representative in various microelectronics industry working groups.

Frank Gayle

Frank Gayle, ScD 
NIST Office of Advanced Manufacturing 

Bio

Deputy Director

Dr. Frank W. Gayle is Deputy Director of the Office of Advanced Manufacturing at the National Institute of Standards and Technology, and also Deputy Director of the Advanced Manufacturing National Program Office.

Dr. Gayle started his career with 11 years in industry, developing aerospace alloys and their manufacturing scale-up processes. He then joined the NIST Metallurgy Division where he spent much of his career, ultimately as Division Chief. As Chief, Frank developed major programs in energy, microelectronics, and mechanical properties.

From 2002 through 2007, Frank headed the team of experts investigating the structural steel involved in the collapse of the World Trade Center towers on September 11, 2001. The NIST investigation led to major changes in building codes across the globe, dramatically enhancing building safety.

Francisco Ibanez

Francisco J. Ibáñez
European Commission

Bio

Senior Expert, Microelectronics and Photonics Industry
DG CONNECT

Francisco J. Ibáñez holds university degrees in Engineering and Solid-State Physics (Autonoma University, Madrid) and Masters in Communication Networks and Signal Processing (Polytechnic University, Madrid), Business Administration (Catholic University of Leuven) and Information Society and Knowledge (Open University of Catalonia).

Prior to joining the European Commission, he was active in semiconductors research (Bell Labs, US) and had a number of industrial assignments, including process and product engineering in microelectronics design and fabrication (AT&T Microelectronics, Lucent Technologies).

At the European Commission he had responsibilities in different R&D and policy areas, including Future and Emerging Technologies (FET) and Networks and Communications. He is currently involved in the EU Chips Act as part of the Microelectronics and Photonics Industry unit within DG CONNECT. 

Meredith

Meredith LaBeau, Ph.D.
Calumet  

Bio

Chief Technology Officer

Dr. Meredith Ballard LaBeau is the Chief Technology Officer and on the strategic leadership team at Calumet Electronics, a leader in manufacturing high-performance Printed Circuit Boards and IC Substrates for defense, aerospace, medical, power-grid, commercial, industrial controls, and space applications.

Meredith is the technical lead and manager of Calumet’s Process Engineering and R&D teams. She also is a member of two international standards committees: IPC and the National Aerospace and Defense Contractors Accreditation Program (NADCAP), an IPC Thought-Leader and plays a critical role in developing standards and PCB manufacturing quality and criteria for the electronics industry.

Matt Neely

Matt Neely 
TTM Technologies

Bio

Director of Process Engineering, North America 

Matt Neely joined TTM Technologies as director of Engineering in 2019 when TTM acquired the assets and technology of i3 Electronics. He spent the bulk of his career working in Printed Circuit Board fabrication at i3 Electronics and Endicott Interconnect Technologies both of which were formerly part of IBM Corp. His roles have been in engineering management, customer program management and process engineering with responsibilities focused on technology growth and new product introduction.

Helen Phillips

Helen Phillips
Northrop Grumman

Bio

Director, Advanced Operations Northrop Grumman Mission Systems

Helen Phillips is the Director of Advanced Operations for Northrop Grumman Mission Systems leading the development of discriminating manufacturing capabilities addressing next generation sensor technology needs. Helen is responsible for a highly motivated team of operations systems engineers who use systems thinking early in the design process to identify opportunities to develop maturation plans ensuring our factory and suppliers are ready for future demands. Helen also manages the planning and execution of Operations NCTA in support of discriminating technologies such as additive manufacturing, advanced packaging, automation and digital thread to improve operational efficiency. 

Jan Vardaman

Jan Vardaman
TechSearch International Inc.

Bio

Founder and President

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. 

She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Kim Ellert

Kim Eilert
BAE System's FAST Labs 

Bio

Technology Development Manager

Kim Eilert is a Technology Development Manager in Advanced Electronics within BAE System's FAST Labs. She is the Integrated Chipset Solutions tech group lead, holds three patents and is an author of several papers describing implementations of passive filters in semiconductors, ceramics, and laminates. She has nearly 20 years of experience in RF and microwave design, focused on filters and packaging.  Previously, Kim held concurrent positions of Business Unit Manager and Senior Principal Engineer at On Semiconductor Corporation. Her responsibilities included ownership of the profit and margin for three technology lines in the foundry business division, cultivation of business relationships, management of marketing and engineering teams, direction of the R&D roadmap for her product lines, and technical design work.  Kim also volunteers with the IEEE Microwave Theory & Technology Society, and is a voting member of its board.  She holds a BSEE from Caltech, and welcomes you to connect with her through LinkedIn.

Haris Basit

Haris Basit
Averatek Corporation

Bio

Chief Executive Officer

Haris Basit is the Chief Executive Officer of Averatek since 2017. Prior to joining Averatek, Haris was CEO at VIASPACE, an alternative energy company. He has also been founder or co-founder of several successful technology-based companies.

From 2004 to 2012 he was co-founder and CEO at Multigig, a fabless semiconductor company that was sold to Analog Devices. He has also held senior level positions at Lucent Technologies (Bell Labs division); Rockwell International; and at IBM Research Labs.

Kevin Engel

Kevin Engel
Amkor Technology, Inc

Bio

Corporate Vice President, Flipchip / Wafer Level Business Unit

Kevin Engel currently serves as Corporate VP, Flip Chip/Wafer Services Business Unit and President of General & Supervisory Board of Amkor Technology Portugal. Kevin joined Amkor in 2004 as part of the acquisition of Unitive Electronics. 

Amkor is a leading provider of outsourced semiconductor packaging and test services.  In his role, Kevin is responsible for multiple advanced packages including advanced flip chip, bumping, fan-out, high-density heterogenous integration solutions and test. These packages support a broad IDM, Fabless and Foundry customer base in the Automotive, Communications, Computing and Consumer markets. Manufacturing of these products occurs in South Korea, Japan, China, Taiwan and Portugal.

He has held various management positions in the semiconductor manufacturing and packaging industry for more than 25 years.

Michael Gleason

Michael Gleason
GreenSource Fabrication LLC

Bio

Director of Product Development

Michael Gleason is the Director of Product Development for GreenSource Fabrication in Charlestown, New Hampshire.  Since early 2006, Michael has held numerous management positions in the domestic PCB fabricator landscape. He joined GSF in 2021 after a five-year stint at Draper Laboratory as their PCB manufacturing SME where his primary focus was on bleeding edge PCB design and DFM supporting uHDI, organic substrates, SLPs and electronics packaging. 

Mario

Mario Ibrahim
AT&S

Bio

Business Development Manager

Mario Ibrahim is a Strategic Business Development Manager at AT&S. He is engaged in AT&S’s advanced IC substrate and packaging development activities. He follows the semiconductor market trends, develops new businesses and helps in building the company’s future strategies.

Prior to AT&S, Mario was engaged in Advanced Packaging activities at Yole Développement (Yole) where he developed technology and market reports in addition to custom consultancy studies covering advanced packaging topics. Mario was engaged for 5 years in test activities development for LEDs at Aledia and oversaw several advanced packaging R&D programs. He spent three years at STMicroelectronics (Grenoble), where he contributed to test benches park automation within the Test & Validation team.

Tom McCarthy

Tom McCarthy
AGC Taconic 

Bio

Vice President of Innovation 

Thomas McCarthy started his career in the chip packaging/circuit board industry at AlliedSignal in 1993. Tom later spent 20 years at Taconic having various positions including Director of Engineering and VP of Business Development.  AGC purchased Taconic’s Advanced Dielectric Division in 2019 after which Tom continued to manage the North American RF business for AGC. Tom has spent his entire career developing composite materials and continues to manage research into new thermoset composite material for low loss, low DK applications.   

Naoki Okuno

Naoki Okuno
OKUNO

Bio

Chief Administrative Officer

 

Growing up in a family-owned metal finishing chemical company that was a dominant force in Japan and Asia, Naoki traveled the globe meeting, working, and often collaborating with many of the strongest and most technologically advanced companies, with the goal of acquiring and developing next generation technology for global markets.

His resume includes positions in Sales & Marketing, Technical support and business management in Asia, Europe, the United State and South America. Naoki is currently on the board of directors of Okuno Chemical Industries and is responsible for creating and exploring future businesses in growing markets such as semiconductors and new technologies to achieve SDGs.

Tom Rucker

Tom Rucker, Ph.D.
Intel Corporation

Bio

Vice President Technology and Development

Dr. Tom Rucker is vice president in Technology Development and director of Assembly and Test Technology Development Integration at Intel Corporation. He is responsible for the yield, development and initial production of Intel’s assembly and test process technologies.

His career at Intel has included responsibility for the development and initial production of Intel’s first-generation wafer bumping technology and first-generation flip-chip technology.

 

Tom has also managed Intel’s factory automation organization, where he oversaw the development of software, hardware and material-handling solutions for factories. He also previously served as director of the Digital Home Group, with responsibility for platform hardware and software solutions for networked media products and digital TVs based on Intel silicon.

Charles Woychik

Charles Woychik, Ph.D.
SkyWater Technology 

Bio

Senior Director, Advanced Packaging Platforms

Dr. Charles G. Woychik is the Senior Director of Advanced Packaging Platforms at SkyWater Technology in Kissimmee, FL. 

Previously he was the Chief Scientist at i3 Microsystems in St. Petersburg, FL.  He was the Senior Director of 3D Technology at Invensas Corporation and was a Senior Scientist at GE’s Global Research Center.  He began his career at IBM Endicott, NY where he held both engineering and managerial positions. His area of expertise is materials and processes for electronics packaging.  He has 123 issued US issued patents to his credit. 

Walter Moser

Walter Moser
Director Public Affairs Global

Bio

AT&S

Walter Moser has more than 30 years of experience in the innovative electronic business environment. He built up his knowledge of international management by founding legal entities and organizational units in Europe, Asia and the USA. In an expat assignment in Shanghai and Hong Kong, he not only built up the sales organization for AT&S in Asia, but also the organizational basis of AT&S Asia Pacific in Hong Kong.

Originally trained as a mechanical engineer, he holds a degree in international business. His responsibilities within AT&S AG over the past three decades include general management positions at AT&S Asia Pacific, AT&S Americas LLC and AT&S Germany. In the last ten years he was CSO of the Business Unit AIM (Automotive, Industrial, Medical) with plants in Austria, India and Korea.

In 2021, he took over the position of Director Public Affairs Global for AT&S AG.

 

Matt Bergeron

Matt Bergeron 
Integra Technologies 

Bio

VP Business Development 

Matt Bergeron is VP of Business Development at Integra Technologies. He was previously CEO of CORWIL Technology, the largest North American outsourced semiconductor assembly and test (OSAT), until its acquisition by Integra. Matt’s 30+ year career includes President of WELLS-CTI, Inc, a semiconductor test and thermal management company; CEO of e2E Corporation, a global printed circuit board design and simulation company; and President of Praegitzer Industries, Inc, one of the Top 10 Circuit Board manufacturers with sales of over $220 million.

Jim Fuller

James W. Fuller, Jr.
Sanmina

Bio

Vice President, Engineering and Technology Development

Jim is currently Vice President of Engineering and Technology Development for Sanmina’s PCB Division, responsible for product introduction, process implementation and manufacturing optimization. He previously worked for Endicott Interconnect where he held several positions including Vice President and General Manager of Fabrication, and Vice President of Engineering & Technology. He was Senior Engineering Manager for IBM, with Manufacturing Engineering responsibility for all products manufactured in Endicott. Jim holds or co-holds 16 US patents and has published several papers. 

Thomas Gottwald

Thomas Gottwald
Schweizer Electronic 

Bio

Vice President Technology

Thomas Gottwald started his career at Schweizer Electronic AG in 1991. He began as a project manager in process technology, was Head of Product management, was appointed Director of the Innovation Center in 2011 and as a member of the Schweizer Leadership Team. In his current role as Vice President Technology, he is responsible for the departments Front End, Product Management, Embedded Power Solutions and Innovations. His focus is on embedding technologies, power electronics, electronic materials, and thermal management.

Deepal Kulkarni

Deepak Kulkarni, Ph.D.
AMD

Bio

Fellow, Advanced Packaging Substrate Technology Development

Dr. Deepak Kulkarni is a Fellow at AMD. Deepak currently manages the advanced packaging, technology integration team. Over the last 17 years, he has held several leadership positions driving technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds eight patents and 19 publications on various aspects of packaging.

Dale McHerron

Dale McHerron, Ph.D.
IBM Research, AI Hardware Center

Bio

Senior Manager, Heterogeneous Integration Research

Dr. Dale McHerron is currently Senior Manager at IBM Research based in Albany, NY with responsibility for IBM’s Heterogeneous Integration Research Program and project leader in the IBM AI Hardware Research Center. 

Over his 30-year career at IBM, Dale has held various technical, managerial, and business development positions in both advanced packaging and CMOS logic R&D. 

In 2007, he transitioned to the IBM Albany Research lab where he has initiated and led research projects in logic scaling, heterogeneous integration, and has played a key role developing the IBM collaborative research ecosystem in Albany.

John Ostrowski

John Ostrowski
Lam Research

Bio

Managing Director, SABRE 3D

John Ostrowski has 32 years experience in the semiconductor industry and 26 years in electroplating. John is Product Line Head for SABRE 3D at Lam Research, where he sets the strategic path for continued market share increase and improved financial performance. Prior to becoming the product line head for SABRE 3D, John worked for over 20 years in different positions within the Electrofill Business Unit. Since 1996, John has been part of the SABRE development team, first as Electrical and Systems Engineer, and later as Program Manager tasked with ensuring successful penetration into a large device manufacturer. From this experience it was a natural transition into the management of the Global Product Support team for the Electrofill BU and then taking over the Director of Engineering position for SABRE 3D. John holds 8 US Patents.

Devanand Shenoy

Devanand Shenoy, Ph.D.
Office of the Under Secretary of Defense for Research and Engineering & Office of the Deputy Chief Technology Officer for Critical Technology

Bio

Principal Director for Microelectronics
Director, Defense Microelectronics Cross-Functional Team

Dr. Devanand Shenoy joined the Office of the Under Secretary of Defense for Research and Engineering as the Principal Director for Microelectronics in July 2021. In this role, Dr. Shenoy is responsible for leading the Department of Defense’s research and engineering efforts in Microelectronics.

Dr. Shenoy previously served as the Director of Microelectronics Innovation and as Director of Advanced Technologies at the University of Southern California’s Information Sciences Institute. His career also includes serving as Chief Engineer in the Advanced Manufacturing Office at the U.S. Department of Energy; serving as Senior Advisor at the Manufacturing and Industrial Base Policy (MIBP) Office within the Office of the Secretary of Defense (OSD) as a detailee from the Army Night Vision and Sensors Directorate (NVESD) at Fort Belvoir where he helped develop a public-private partnership in Photonics that led to the creation of the AIM Photonics Institute. His career includes other roles in defense and commercial applications.

Todd Younkin

Todd Younkin, Ph.D.
Semiconductor Research Corporation (SRC)

Bio

President and CEO

Dr. Todd Younkin is the President & CEO of SRC, where he leads a ~$90M/yr. global research agenda supported by ~3k academic and industrial researchers, 27 international companies, and 3 U.S. government agencies (DARPA, NSF, and NIST). Prior to becoming SRC’s CEO, Dr. Younkin worked at Intel from 2001-2020, with research and development experience that spanned Intel’s 0.18um to 5nm nodes and a variety of Intel business units.

With his leadership, SRC released its 2030 Decadal Plan for Semiconductors, and has called for greatly increased federal investments throughout the decade to establish a smarter pipeline for semiconductor R&D. This drove and resulted in the passage of the CHIPS and SCIENCE ACT of 2022 by Congress and President Biden on August 9th, 2022.

Todd is excited by the worldwide call for a renewed investment in semiconductor materials, hardware, and design, as well as the emphasis on education, workforce development, and environmental sustainability. Only by investing in a bright, collective future, will we rise to the meet the opportunities presented by the next industrial revolution.

REGISTRATION

Your registration includes a two-day conference with 28 speakers and eight sessions, three keynotes, breakfast receptions, lunches and an evening networking reception!

Price per person: $895

Academic Faculty are eligible to receive 50% off the above price. Please contact Kim DiCianni at  KimDiCianni@ipc.org to receive your discounted rate. 

Register

SPONSORSHIP OPPORTUNITIES

Premier Sponsor

Cost: $15,000 

Benefits include:

  • Opportunity to present a 2-minute video to attendees during attendee welcome address
  • Opportunity to distribute company brochures to be placed on seats or tables during the welcome address
  • Social media spotlight on all IPC social media platforms which include posts on: 
    • Facebook
    • LinkedIn
    • Twitter
  • Company name and logo predominantly displayed on:
    • Event website
    • Pre-event promotions/emails
    • Signage at the event
  • Three complimentary registrations to attend the event
Supporting Sponsor Plus

Cost: $10,000

Benefits include:

  • Social media spotlight on all IPC social media platforms which include posts on
    • Facebook
    • LinkedIn
    • Twitter
  • Company name and logo predominantly displayed on:
    • Event website
    • Pre-event promotions/emails
    • Signage at the event
  • Two complimentary registrations to attend the event
Supporting Sponsor

Cost: $5,000

Benefits include:

  • Company name and logo predominantly displayed on:
    • Event website
    • Pre-event promotions/emails
    • Signage at the event
  • One complimentary registration to attend the event

Please reach out to our sponsorship sales representative, Mike Stone at MikeStone@ipc.org or call +1 847 597 2866 to reserve your sponsorship. Sponsorship opportunities will be available on a first come-first serve basis, so please reserve your opportunity today. 

TRAVEL AND HOTEL INFORMATION

Travel Options

Nearest Airports

Nearest Amtrak/ MARC/ VRE Train Station

Hotel Accommodations Options

IPC offers this list of hotel accommodation options for your consideration. You are welcome to book your accommodations at any hotel that you prefer. Please call the hotel of your choice directly for rates and availability. 

Kimpton Hotel Monaco (Symposium Location)
700 F Street NW
Washington, D.C. 20004
Hotel Website
Reservations number: (800) 649-1202

Cambria Hotel Washington DC Capitol Riverfront
69 Q Street, SW
Washington, DC 20024
0.9 miles from the Kimpton Hotel Monaco (conference location)
Hotel Website

ABOUT THE EVENT ORGANIZER 

About IPC
IPC (www.IPC.org) is a global industry association based in Bannockburn, Ill., dedicated to the competitive excellence and financial success of its nearly 3,000 member companies which represent all facets of the electronics industry, including design, printed board manufacturing, electronics assembly and test. As a member-driven organization and leading source for industry standards, training and education, industry intelligence and public policy advocacy, IPC supports programs to meet the needs of an estimated $2 trillion global electronics industry.

Cancellation Policy:
If you are unable to attend the conference, you may send a coworker in your place. Please notify us of name changes as soon as possible. Registrants who cancel by September 30, 2022, will be refunded in full, but those who cancel after that deadline will be responsible for the full registration fee. Sponsors who cancel by September 30, 2022 will incur a $100 cancellation fee and no refund will be issued for sponsors that cancel after the deadline. If you need to change your registration or cancel, please email Kim DiCianni at KimDiCianni@ipc.org

Application of Dielectric Spectroscopy (Ds) for Quality Control of Solvent-Borne Conformal Coatings

Member Download (pdf)

The viscosity of conformal coatings is critical in producing consistent and reliable applications of coating onto a printed circuit board (PCB). A conformal coating that has experienced moisture absorption, premature cure, solvent evaporation, or has unexpected solids content may affect the viscosity and ultimate thickness of the coating or integrity of the PCB. As a result, these variations may also produce defects such as orange peeling, delamination, air entrapment, or scavenging. This study aims to develop a method using dielectric spectroscopy (DS) for measuring the fitness for use of solvent-borne conformal coatings.

In this work, the solids content of multiple types of coatings was altered by the addition of thinner at dilutions of 100% to 50% coating. In addition, a few 100% coatings were exposed to an accelerated aging process to allow for premature curing to occur. Samples from each experiment were measured using DS and a viscometer to correlate the dielectric and mechanical behaviors of these materials. The impedance spectra of all dielectric measurements were fit using an equivalent circuit model. The resulting values, defined as the Coating Consistency Index (CCI), were derived from the time constants of this model; changes in CCI were correlated with changes in coating viscosity. Therefore, DS can be used as a quality control method to monitor the effects of premature cure and the addition of thinner to solvent-born conformal coatings in relation to viscosity.

Key words: conformal coating; quality control; viscosity; thickness; solids content; premature cure; dielectric spectroscopy; defects; coating consistency

Author(s)
Wilson Chen, Morgan Miller, Ian Miske, Christopher Frederickson, and Dongkai Shangguan
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

North American PCB Industry Sales Up 17.1 Percent in June

IPC Releases PCB Industry Results for June 2022

IPC announced today the June 2022 findings from its North American Printed Circuit Board (PCB) Statistical Program. The book-to-bill ratio stands at 1.03.

Total North American PCB shipments in June 2022 were up 17.1 percent compared to the same month last year. Compared to the preceding month, June shipments rose 26.3 percent.

PCB year-to-date bookings in June were down 4.1 percent compared to last year. Bookings in June increased 14.4 percent from the previous month.

“Shipments in the PCB sector are improving, suggesting supply chain challenges might be abating. Shipments are up 10.4 percent over the last three months compared to a year ago,” said Shawn DuBravac, IPC’s chief economist. “Orders appear to be stabilizing at a high level. Orders are off 1 percent over the same period, but up 23.6 percent compared to pre-pandemic levels.”

PCB book to bill chart 1 June 2022
PCB book to bill chart 2 June 2022

Detailed Data Available

Companies that participate in IPC’s North American PCB Statistical Program have access to detailed findings on rigid PCB and flexible circuit sales and orders, including separate rigid and flex book-to-bill ratios, growth trends by product types and company size tiers, demand for prototypes, sales growth to military and medical markets, and other timely data.

Interpreting the Data

The book-to-bill ratios are calculated by dividing the value of orders booked over the past three months by the value of sales billed during the same period from companies in IPC’s survey sample. A ratio of more than 1.00 suggests that current demand is ahead of supply, which is a positive indicator for sales growth over the next three to twelve months. A ratio of less than 1.00 indicates the reverse.

Year-on-year and year-to-date growth rates provide the most meaningful view of industry growth. Month-to-month comparisons should be made with caution as they reflect seasonal effects and short-term volatility. Because bookings tend to be more volatile than shipments, changes in the book-to-bill ratios from month to month might not be significant unless a trend of more than three consecutive months is apparent. It is also important to consider changes in both bookings and shipments to understand what is driving changes in the book-to-bill ratio.

IPC’s monthly PCB industry statistics are based on data provided by a representative sample of both rigid PCB and flexible circuit manufacturers selling in the USA and Canada. IPC publishes the PCB book-to-bill ratio by the end of each month.

Comprehensive SIR Testing for Platform Release in the Automotive Industry

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A comprehensive SIR test-protocol for the release of materials and processes in the automotive industry is presented. In this way, by a combination of comprehensive SIR testing and intensive humidity testing during product validation objective evidence for achieving humidity robust electronic control units is derived. For comprehensive SIR testing the content of IEC 60064-3-4 which describes conditions for environmental testing was reviewed. It could be shown that for open PCBAs the recommended cyclic damp heat condition IEC 60068-2-30 is appropriate. It could also be demonstrated that a higher load as given by IEC 60068-2-38 is already overstress for open PCBAs but suitable for testing of PCBAs in a housing. The effect of self-heating of units was additionally investigated. A very significant effect was found by superimposing the heat dissipation as known from real products on SIR test boards inside a housing. A clear shift from conditions that lead to failures by electrochemical migration in the unheated case towards humidity robust designs in the heated case are shown by SIR measurements.

Author(s)
Dr. Lothar Henneken, Robert Bosch
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

A Critical Analysis of CAF Testing-- Temperature, Humidity, and the Reality of Field Performance

Member Download (pdf)

As Conductive Anodic Filament (CAF) testing on Printed Circuit Boards (PCBs) approaches 50 years of industry attention, the chemistry of formation in the lab environment is well documented, significant resources have been expended in passing the lab test, and new efforts are in progress to make the test even more difficult to pass with voltages up to 1000v. But what about the operating environment for this shorting mechanism— to what extent is CAF a “field fail” risk today? Is it possible to prove that text book CAF failures are actually impossible in today’s typical office system environment? With future PCB technology driving progressively smaller via-via spacings, is there a point where tomorrow’s reliable product will never pass today’s CAF test? Either way, considering CAF testing as a subset of the broader Insulation Resistance (IR) test, what are the shorting failure mechanisms the industry should be concerned about and what is the best test for them?

This paper surveys 40 years of experience in a reliability and failure analysis lab with IR testing, product reliability qualifications, and field return forensics. Shorting based field failures are described and ranked based on impact, risk, and changes over time with industry wide improvements in electrical test and laminate materials. Two test methods 65C/85%rh and 50C/80%rh are compared in terms of time to fail and resulting failure mechanisms. Also presented is a data-generated temperature and humidity (T&H) model from a CAF prone material using a unique test vehicle, along with data for the important question of CAF formation humidity threshold. The IR/CAF fire triangle of moisture + path + ions is discussed-- how it perfectly explains all types of PCB insulation resistance failures. The CAF triangle is further validated by test results from purposely populating an office system with pre-soaked CAF prone boards, and by data for this question: is the T&H part of the CAF test reversible? The criticality of T&H control in accurate CAF testing is demonstrated with chamber measurements and test data. Finally, the importance of finding the right IR/CAF test for future HDI/tight grid technology is addressed.

Author(s)
Kevin Knadle
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

North American EMS Industry Down 7.6 Percent in June

IPC Releases EMS Industry Results for June 2022

IPC announced today the June 2022 findings from its North American Electronics Manufacturing Services (EMS) Statistical Program. The book-to-bill ratio stands at 1.39.

Total North American EMS shipments in June 2022 were down 7.6 percent compared to the same month last year. Compared to the preceding month, June shipments increased 9.6 percent.

EMS bookings in June decreased 13.9 percent year-over-year and increased 12.0 percent from the previous month.

“The headlines seem to be focused on recession, but the most recent results from IPC's North American EMS statistical program tell a different story,” said Shawn DuBravac, IPC chief economist. “Yes, order flow is slowing, but orders remain strong. Orders through the first 6 months of 2022 are down 6.4 percent compared to a historically strong 2021. But orders are up 8.4 percent compared to the first six months of 2019. Orders continue to outpace shipments, suggesting supply chains are still tight.”

June 2022 EMS book to bill chart

Detailed Data Available

Companies that participate in IPC’s North American EMS Statistical Program have access to detailed findings on EMS sales growth by type of production and company size tier, order growth and backlogs by company size tier, vertical market growth, the EMS book-to-bill ratio, 3-month and 12-month sales outlooks, and other timely data.

Interpreting the Data

The book-to-bill ratios are calculated by dividing the value of orders booked over the past three months by the value of sales billed during the same period from companies in IPC’s survey sample. A ratio of more than 1.00 suggests that current demand is ahead of supply, which is a positive indicator for sales growth over the next three to twelve months. A ratio of less than 1.00 indicates the reverse.

Year-on-year and year-to-date growth rates provide the most meaningful view of industry growth. Month-to-month comparisons should be made with caution as they reflect seasonal effects and short-term volatility. Because bookings tend to be more volatile than shipments, changes in the book-to-bill ratios from month to month might not be significant unless a trend of more than three consecutive months is apparent. It is also important to consider changes in both bookings and shipments to understand what is driving changes in the book-to-bill ratio.

IPC’s monthly EMS industry statistics are based on data provided by a representative sample of assembly equipment manufacturers selling in the USA and Canada. IPC publishes the EMS book-to-bill ratio by the end of each month.

Using Machine Learning for Anomaly Pattern Recognition in Manufacturing Processes

Member Download (pdf)

As the manufacturing sector is under constant pressure to satisfy customers’ demands in a competitive market by applying complex processes to meet manufacturing cost and schedule goals, the need to identify quality variables within processes is occurring at a faster rate. Locating the source of process variations becomes more challenging for engineers. Each day, the manufacturing sector generates tremendous amounts of data that provide valuable information. This data is crucial to supporting strategic business operations decision-making. Traditional ways of data interpretation are labor intensive and time consuming. Failure to accurately and precisely translate data will lead to subjective “opinion” or “speculation-based” decision-making.

In this paper, we will review general opportunities for the application of machine learning (ML) algorithms and methods to the test data troubleshooting process. A method is developed for analyzing data and identifying patterns that are consistent with poorly performing units. This method uses a “quasi-supervised” learning technique to identify drivers of variance within a dataset, visualize the trends among the primary drivers of variance, and establish some screening limits based on those trends. The method employs Principal Components Analysis (PCA) to review patterns, trends, and uses some knowledge of better or worse performing groups. The output is a set of screening limits that characterize parts likely to have similar performance. The method provides clear knowledge, visualization, and understanding of the trends that are driving failures or poor performers.In addition, it does not require the rigorous data capture that a true supervised learning method. This method can be used on any dataset with observations in the rows and attributes/variables in the columns if there is some knowledge of an identifiable batch that is better or worse than the others. A performance characterization on a batch of units was successfully performed to identify the anomalies within a dataset.

Author(s)
Shadi Kuo, Richard Witmer and Martin Goetz
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022

Towards Artificial Intelligence in SMT inspection processes

Member Download (pdf)

To ensure the highest possible quality standards in automotive electronics production, an extensive implementation of testing and inspection systems throughout production is mandatory. In SMT production optical inspection systems are the standard technology for evaluation of quality in SMT soldering processes.

To ensure the highest possible level of quality, these systems are enhanced by human verification experts that review results from the automated process and thereby ensure a high level of quality while minimizing production losses through false calls.

In this contribution we introduce an Artificial Intelligence platform designed for application in SMT inspection processes, enhancing and eventually outperforming the human verification operator. The design of the platform is chosen to be process agnostic and can be applied in any quality inspection process that relies on visual information in pictures.

For the design of the platform, we have collected more than 1 billion solder joint pictures and labels from the shop floor as the foundation for the development work. To ensure proper training results, we have worked with a team of soldering experts to ensure correct labeling on a significant portion of these pictures.  Based on this data we designed deep learning algorithms that are capable of properly clustering the error images into the error classes predefined by internationally accepted standards and reliably identifying the large class of false calls. 

To make the algorithms usable for production and specifically to enable non-AI-experts to work with the algorithms, we embedded them into a tool suite based on apps that are easy to use for soldering experts. In the applications, datasets can be handled, new decision models can be trained, neural network quality can be evaluated and eventually the decision models can be deployed to the production line. On the shop floor the decision model can support the operator with suggestions, or it can also completely take over the task of verification in certain scenarios. 

The solution presented here is in practical use on large scale and therefore the contribution offers a theoretical approach to the topic, an implementation example with a platform solution and a view on the business impact of the solution.

Author(s)
Mario Peutler, Michael Boesl, Johannes Brunner, Dr. Thomas Kleinert
Resource Type
Technical Paper
Event
IPC APEX EXPO 2022