In this study, a patent-pending new solder paste material has been developed for assembly of System in Package (SiP) with outstanding slump resistance without compromising the paste volume printed, and the solder joint service temperature. In the fine pitch solder paste using medium temperature solder powder (MTSP), low melting solder powder (LMSP) was introduced. At printing, the powder mixture behaved as regular fine-pitch solder paste. Upon heating, the LMSP melted and formed “Powder Cluster” with surrounding MTSP. The Powder Cluster resisted slump, thus avoided solder bridging, consequently enabled high yield of assembly. When 58Bi42Sn was used as LMSP in SAC305 solder paste, the desired LMSP content was found to be no less than 4% w/w of solder paste for great slump resistance at 100°C, 150°C, and 200°C, and no more than 8% w/w of solder paste for the 1st sign of melting of reflowed solder to be no lower than 179°C. The slump resistance achieved at 100°C which was lower than the melting temperature of 58Bi42Sn was attributed to Powder Cluster formation due to solid-state diffusion. The overall metal load tested was found to be acceptable at 82% w/w and can be further optimized for better print and slump-resistance performance. Higher print thickness and higher heating temperature resulted in a higher slump rate, suggesting the choice of LMSP and MTSP would affect the slump resistance potential. Print pattern was found to affect slump resistance through “Paste Crowdedness” factor, which can be used as a tool for assessing the potential of slump rate during stencil design phase.

Key Words SiP, solder paste, powder cluster, paste crowdedness, slump resistance, anti-slump, low melting solder powder, LMSP, medium temperature solder powder, MTSP

Use of low-cost Aluminum based flexible printed circuit boards or Al-PCBs has been growing in popularity. Integrating them with conventional Copper based PCBs or Cu-PCBs is essential for their large-scale adoption. This is because most complex electronic systems that use Al-PCBs require them to be connected to other PCBs for an electrical or data connection. Soldering is the preferred method for mounting Surface Mount Devices (SMDs) and connecting circuit boards. But that brings in processing challenges.

Soldering to aluminum requires an additional surface treatment or the use of conductive epoxy. These are cost-prohibitive and have reliability challenges. And existing products like solders, fluxes, tack agents, cleaners etc. are formulated for Cu-PCBs and do not work on aluminum.

A Surface Treatment technology will be presented that addresses all these constraints. Once printed on aluminum using conventional printing techniques such as screen, stencil etc., it is cured thermally in a convection oven at low temperatures, leaving a non-conductive deposit on the pads. This is followed by conventional process i.e. print solder over the treated pads, place components and then reflow resulting in finished Al-PCBs. Surface Treatment can also be used to solder Al-PCBs to flexible and rigid Cu-PCBs.

This is a paradigm shift in the industry which opens up many new applications, including those in the RFID, LED, and automotive industries. An increasingly popular method to make flexible circuits use Aluminum on PET (Polyethylene terephthalate) or Al-PET substrates. This paper provides cross-sections and shear data on soldered joints, including joints for Al-PET to Cu-PCB, and also for Al-PET to Cu-pigtails using aluminum metallization with low-temperature Bi-Sn-Ag solders. It will also show other processes such as hot-bar soldering to achieve good solder joints between Al/PET and Cu-PCBs.

The assembly of complex optical systems such as objective lenses for smartphone cameras, autonomous driving sensors / cameras, and light detection and ranging (LiDAR) require precise alignment during their production. This is accomplished via an Active Alignment process utilizing real-time measurements alongside light curable adhesives to fix the components in-place once aligned. The adhesive is critical towards maintaining alignment, bonding structural components, and fixing sensors and modules to the PCB substrates. Active alignment adhesives must conform to strict technical requirements: minimal volumetric shrinkage, low CTE, rapid cure, and high Tg. UV-curable cationic epoxy-based adhesives deliver on these requirements and allow for the assemblies to perform at a more demanding level as well as driving the assembly process efficiencies to significantly increase capacity and productivity. Their physical and mechanical properties will be discussed alongside applications and future developments.

Printed Circuit Structures (PCSs) have the potential to revolutionize next generation printed circuit boards (PCBs) and electronics packaging. Almost every product available today contains sensors, electronics and radios and the growth of the Internet of Things (IoT) is one of the driving forces for this. The circuits are composed of traces, vias, passive components, active components, antennas and more. The PCB or flex circuit must then be inserted into or on an object, and if there are multiple circuits, wires are used to electrically connect them, and bolts and glue are used to mechanically secure them. The extra weight and volume required account for the mismatch in shape and the need to physically access the boards for assembly in the object will often mean the wasted volume for a circuit can be 100 to 1000 times larger than the circuit itself. PCSs have the potential to eliminate that wasted volume, reduce the weight, and increase the number of electronic functions per volume. Even more, the third dimension gives more degrees of freedom for circuit design and allows circuits to utilize physics more effectively than planar designs. We will present a timeline for PCSs, the challenges in software, process and hardware, the advantages, state-of-the-art in PCS today, working demonstrations and the required improvements for PCSs to ultimately exceed the performance of traditional PCBs and flex circuits.

In the LIFT (Laser Induced Forward Transfer) technology, a material, evenly coated on a transparent carrier film, passes under a laser. The laser applies a short burst of energy to it. This releases perfectly consistent drops of material onto the substrate below. The material drops can then be sintered or cured inline, in the same machine. A great benefit is that this technology works for solder and polymers as well as for metals and ceramics. Multiple materials can be printed at the same time. This new technology opens the way to new advanced applications and the fabrication of innovative materials and novel applications. LIFT systems can work with many materials currently on the market and will also leave great freedom to innovate to both material engineers and chemists: they will be able to create products with significantly better properties than those achievable with current 3D printing technologies due to the low constraint requirement on the printed material. Viscosities can exceed 300,000 cPs and fillers of more than 40μm can be added. The current paper deals with one application of this technology, an innovative approach to manufacture circuit boards with the speed of printing.

In the last few years there have been concerns in the industry, especially in products requiring high reliability when using microvia structures. As a result, many fabricators have been mandating push back on very complex high layer count designs.

This has resulted in very conservative rules for designers to use based on the limitations of fabricator capability. Some fabricators have also struggled to ensure that even simple structures are built reliably and repeatably.

This study was designed to look at materials which would ensure that more complex structures could be built reliably. Thinner glass reinforced dielectric layers have been developed for build-up multilayer. These tend to be resin rich in order to flow and encapsulate heavier plated-up copper features. Thin fiberglass-reinforced dielectrics can have issues caused by the lack of flow of ceramic-filled resin from side to side through spread weave fiberglass. These resin rich and higher resin-to-glass ratio dielectric materials are less desirable for the manufacture of reliable stacked microvias in part due to their higher X, Y, and Z axis rates of expansion.

Current industry practice has been to limit designs to staggered microvias and 1-2 layers of stacked microvias. This study shows how a thin, non-reinforced dielectric layer can be used and optimized for stacked microvias that demonstrate solid thermal reliability up to 4 levels of high density interconnect (HDI). It also shows that there seems to be no indication yet of a ceiling on how many layers could be used.

The paper will cover

1) objectives of the study;

2) some of the properties of the material used;

3) tests and results;

4) discussion and conclusions as well as further studies.

Plated and filled microvias are a common feature in modern PCBs, so much so, that they are now considered as the industry norm as a means of achieving high-density designs for modern mobile devices. However, over the last five years or so, there has been growing concern regarding their long-term reliability performance when in a multiple stacked configuration.

Blind microvias (BMV) have potentially complex metallurgical structures, with multiple interfaces located around the target pad to via joint. Where reported, failure analysis typically identifies only two major types of crystal structures formed at the BMV base, yet there is little or no work which discusses how or why such structures have likely developed.

This paper reviews the observed microstructures typically found within filled BMVs and offers proposals on how such structures form. Immediately after deposition, and in the case of electrolytically formed Copper, for some time afterwards, plated layers have a fine nanocrystalline or amorphous structure, and typically undergo significant recrystallisation, which is critical in determining the properties of the final BMV. Herein, we outline “bottom up” and “top down” recrystallisation, which respectively lead to a fully epitaxial interface, or one with significant alignment of Cu-grain boundaries. Using a range of inspection techniques, we offer mechanisms by which such structures develop, which can typically be as a result of process related issues, or through the interaction with plating additives. We then discuss some preliminary results relating the two identified grain structures to mechanical BMV performance and confirm that a region of aligned grain boundaries is detrimental to BMV reliability.

Traditional PCB fabrication technology incorporates copper-plated vias after each press lamination connecting with microvias or mechanical vias. Conductive epoxy or transient phase conductive material are considered instead of copper plating where the board construction undergoes a one-press lamination cycle. The price per board was comparable between PCB fabrication methods; however, the transient phase conductive material process yielded a much shorter turn time (2 weeks versus 10 weeks). Radios tested were close enough in design to provide an opportunity to compare product performance between two fabrication methods. The following report details the findings of the product data, bench evaluations on specific nets, and reflow coupon data collected in production. Development Engineering, PCB Layout group, and Quality collectively established qualification steps for using transient phase conductive material in production.

The steps were:

1) Electrical comparison tests between the two mentioned designs.

2) Accelerated Life Tests between designs.

3) Test to failure and root cause analysis of two designs.

This paper contains the findings of step 1.

Microvia technology has been used in production since the 1990s. In the beginning, the design freedom for HDI PCBs was only limited by the imagination of the designer, resulting in some very ambitions construction. It became apparent quickly that there are limitations on how many microvias one can stack on top of each other and where to place them with respect to the core via. Since product acceptance testing is time constrained, microvia testing is often performed at elevated stress levels that do not directly equate to product life. The aim of the testing is to assert the manufacturing quality of the microvia, under the assumption that a properly manufactured microvia will not negatively impact the reliability of the product.

An extensive test campaign has been executed, covering three levels of microvias in three different materials (high-Tg FR4, RF material and polyimide). Fully stacked, fully staggered and semi-stacked microvia configurations were assessed. For the fully staggered and semi-stacked configuration, the influence of the location of the buried via was investigated. The applied test methods consist of convection reflow assembly simulation followed by air-to-air thermal shock in a HATS2 chamber on daisy chained D-coupon, reflow assembly simulation followed by thermal shock on HATS2 single via coupon, interconnection stress testing (IST) and current-induced thermal cycling. The results revealed both excellent performance of stacked microvias as well as the possibility of the test methods to detect weaknesses in design, material or manufacturing.