The electronics industry is seeing more data being computed through printed circuit boards (PCBs). For example, to support 5G communications, most electronics will need to increase their processing speed compared to the previous system (4G) in order to support data transfer rates. In addition to the communication transfer rates, PCBs are becoming smaller and contain higher layer counts and power requirements. As a result, newer PCBs (such those used in communication devices, MicroLEDs, and Electronic Vehicles), generate more energy and create more heat. Traditional methods for dissipating the heat (such as metal heat sinks, cooling fans, and copper pipes) are becoming less functional since they add weight to devices and can take up valuable real estate. As a result, PCB designs need a practical way of dissipating heat without increasing the device weight and / or size.

PCB designs need unique ways to improve the heat transfer efficiency while maintaining the flexibility to continue miniaturization and enhance data transfer. One solution to this problem is to use a thermally conductive polymeric coating. This coating could be applied in areas where heat dissipation is needed. In theory, this coating could be used under or near components (IC packaging) on the PCB, under or near MicroLEDs, and / or in vias in order to remove heat. For use in these applications, the thermal conductivity of the coating would have to be greater than 6 W/mK and use traditional methods for application. The coating would not add weight to the PCB or take up valuable real estate since it would be applied as a thinfilm and / or be filled in vias which are already part of the PCB design.

Electroless palladium plating has been present in the PCB industry for over 20 years providing highly reliable finishes for high end applications in combination with nickel and gold plating. In addition to the well-established electroless nickel/electroless palladium/immersion gold (Ni/Pd/Au) the palladium/gold finish plated directly on copper has been introduced a couple of years ago (1). As a new alternative finish, it tackles the needs and requirements connected with miniaturization, solder joint reliability and signal transmission. Due to its low overall finish thickness, it is capable to plate fine structures without the risk for excessive plating or short circuits and as a nickel free finish, it offers the additional benefit of being applicable for high frequency applications with low signal loss. The properties of the finial finish itself are defined by the chemical plating process and the reactions taking place during the deposition.

The scope of this paper is the comparison of different palladium electrolytes and their impact on the characteristics of the final finish. In this study, it can be shown that the chemical properties of the plating solution define the material properties of the final deposit and that by adjustment of pretreatment conditions and palladium plating solution, it becomes possible to provide plating solutions which are capable of plating on copper as well as on nickel. Comparison studies for three palladium electrolytes are presented with the focus on solder joint reliability and bonding performance of the plated layer. This includes one electrolyte specifically designed for plating on copper (Pd/Au), one electrolyte specifically developed for plating on nickel (Ni/Pd/Au) and one more universal electrolyte which is capable to plate on nickel and copper. The reliability data are collected in as received conditions as well as after thermal aging. The performance after thermal aging is of particular interest for the palladium/gold finish because of its low deposit thickness and nickel free character, copper migration is suspected as a potential risk to affect the reliability in solder joint formation and wire bonding. In studies of different modifications of palladium/gold deposits, the impact of the layer structure on the barrier properties is investigated.

All data on solder joint reliability, solder wetting and solder bonding performance are correlated to compare the properties of the different finish types and highlight the limitations and benefits of the different solutions.

Key Words

Electroless Palladium

High Frequency

5G

Fine Pitch

Solder Joint reliability

Purpose

One of the challenges of larger parylene chemical vapor deposition (CVD) chambers is what seems to be unpredictable material behavior throughout the working volume. The tight parameters on the state of the substrates, adhesion promoter, and parylene deposition process require informed engineering, even when industry best practices produce problematic distributions of materials.

Results

Transient electrical failures, among other unexpected behavior, that recover over time can be influenced by the method of adhesion promoter introduction, the volume of adhesion promoter used the state of cleanliness of the substrates, the total volume of substrate outgassing, circuit design as well as other factors. Related case studies on the effects of the state of the substrate and conditions before and after coating will be addressed. With very similar products, the same process has worked without issue, countless times.

Outcome

Controlled experiments that vary each of the critical factors have shown how they affect the coating process and product performance. Cross-sectional analysis, FTIR spectroscopy, adhesion tests, process modifications, and substrate concerns will be discussed to illustrate how high-reliability products can be produced in a high-volume manufacturing process using parylene conformal coatings.

The growing use of electronics in every area of our lives around the world has resulted in an increased awareness of potential environmental issues related to their use and disposal. Halogens, which have had various uses in electronics over the years, are known to emit toxic and corrosive gases during the disposal of electronic waste. Across the electronics industry, engineers are tasked with increasing the reliability of components in corrosive and other harsh environments that continue to grow in complexity and decrease in dimension. The use of flexible and highly dense electronics is continuously growing with the advancement of interconnect, microvia and microBGA technologies. While these advancements have offered many benefits to high speed and complex electronics applications, they also have some design and reliability challenges. Some challenges include chemical resistance, electromigration, dendritic growth, solder voids, thermal stress in extreme environments, corrosion and the use of appropriate green materials, including organics, for overall reliability in various operating conditions.

Many organizations have applied pressure to the electronics industry to eliminate halogens completely (e.g., fluorine, chlorine and bromine) from their products. Among the various efforts towards environmentally friendly products, making electronics completely halogen-free has gained significant attention, particularly in Asia and Europe. This initiative even impacts conformal coatings worldwide, on which most electronics rely for their long-term protection, reliability and high performance against water and other corrosive harsh environments. To meet the industry’s current and future requirements, a new halogen-free vapor-phase coating, parylene “H-F”, has been developed. Being a molecular-level vapor phase coating, parylene “H-F” provides protection by reaching into small gaps, crevices and openings, including underneath electronic components.

Our research work demonstrated that this new ultra-thin, completely halogen-free coating provides protection against water splash and water immersion for more than 30 minutes at a depth of 1 m (IPX7) and 1.5 m (IPX8). In addition, it provides resistance to various corrosive chemicals, tin whiskers suppression, and the low dielectric constant and low dissipation factor properties makes it suitable for high frequency (up to 100 GHz) next-generation devices as well.

The excellent IPC-TR-587 technical report, ‘Conformal Coating Material and Application ‘‘State of the Industry’’ Assessment’ delivers the results of a recent major study on conformal coating, outlining an IPC study of major conformal coating types, coating application techniques, and coating cure technologies, characterizing the final film thickness on common component surfaces. It highlights that the nominal thickness applied is not particularly representative of the thickness or coverage of conformal coating materials on the various metallic surfaces. In many cases, the film thickness, although visually not zero, was below the limit of measurement.

In most manufacturing specifications, conformal coating thickness is specified as the thickness of the final polymer film on a flat, unencumbered surface of the assembly, however conformal coating thickness on other assembly and component surfaces is usually not characterized.

In this study, we compare the condensation resistance performance of assemblies coated with state of the art materials to those used in the state of the industry materials. The ‘no-clean’ SMT assemblies were subjected to controlled condensing environments using the National Physical Laboratory’s (NPL) static chamber method, relying on suppressing the temperature of the test board below the dew point, whilst simultaneously measuring Surface Insulation Resistance. Six different coatings were applied and cured, using a variety of common application methods – the same methods used in the state of the industry report, at normal nominal thicknesses, as measured on witness coupons. The coatings are assigned a Coating Protective Index (CPI) score based on their ability to maintain the SIR value of each test site above the widely used 100MΩ pass/fail criterion. A board from each coating set was extensively cross-sectioned after the condensation testing and examined for coating thickness and coverage, to understand how thickness, coverage and the inherent physical material properties combine to determine the Coating Protective Index.

The same 6 coatings were applied to SIR test coupons NPL TB33A (400μm lines, with 200μm spacings) at the same dry thickness. Coupons were tested with and without the same reflowed no-clean paste solder used in the condensation assembly. The SIR was measured throughout a 1000 hour experiment at 85°C/85%RH, a common compatibility test often performed in the automotive industry, to understand the influence of the solder paste / coating compatibility on the coating protective index achieved during the condensation testing.

In the final part of this experiment, the same six coatings were applied to conventional two-dimensional test boards (with and without solder-paste) at the same dry-film thickness, and subjected to immersion in deionised (DI) water at 50V, whilst the coatings resistance was calculated by measuring the leakage current. This allows the comparison of SIR values from condensation experiments with immersion experiments, to better understand whether immersion testing could be a faster & more predictive indicator of coating performance in harsh environments.

A surface insulation resistance study is presented on coated B52-like test boards where a large number of QFN components of different package designs are coated with non-optimal conformal coating process parameters creating bubbles at the QFN leads. Optical inspection showed that bubble sizes have been larger than the lead distance of the QFN, therefore failed according IPC-A-610 acceptance criteria. The bridging situation of the bubbles has been further investigated by means of cross section analysis but lacking a definite result. The electrochemical performance has been tested up to 1000h at elevated humidity condition of 40°C/92%rH at 30V and 65°C/93rH at 20V based on IPC-9202 after thermal pre-aging of the test assemblies. No failures related to electrochemical migration have been found. Further test at cyclic humidity conditions were also passed without any sign of microclimatic issues caused by the bubbles in the coating layer. The material combinations in this study combining conformal coating, solder paste, PCB material and components are found to be robust against microclimate risk from bubbles and voids in conformal coating. Large numbers of QFN show a sufficient electrochemical reliability despite failed in optical inspection. Consequently, the risk of reducing electrochemical performance by bubbles in conformal coatings is overestimated.

A supplier was experiencing laminate cracks in an FR4 dielectric constructed material product after successfully producing this Printed Circuit Board (PCB) for a number of years. The issue was noted during conformance coupon inspection following 3X thermal stress testing, and the cracks were isolated to outer layer dielectrics, layers 1-2 and n to n-1 only. These PCBs have microvias in the outer layers and buried vias from layers 2 to n-1. There are no plated through holes. This PCB had previously gone through a rigid qualification in accordance with MIL-PRF-31032/1 (2020), thermal shock requirements and there were no known significant process changes or material changes since qualification. All materials and critical manufacturing procedures cannot be changed without design agent approval (and potentially some instances requalification). The PCBs are a “hybrid” design, using two unrelated FR4 materials for the outer layers and layers 2 to n-1.

The reasons for the laminate cracks were not clearly evident, but certainly had a thermal component as a factor. The design agent, working with our independent testing agent, developed a finite element analysis (FEA) computer-aided model in an attempt to predict laminate crack initiation and propagation. The model utilized material characterization testing data, which had been performed by the design agent as well as detailed design characteristics of the PCB itself to build a robust model.  This model predicted high stress concentrations from surface pads to buried via locations.

Through design engineering builds of the product, which were based upon predictions of the model, and subsequent environmental testing, the nonconforming laminate cracks were reduced to a conforming condition. This was accomplished through surface pad geometry changes, and shifting of buried vias to maintain a minimum distance between buried vias and surface pads. The FEA model was validated, and is now expected to provide the design agent with a robust predictive design tool to help determine design rules for future enterprises.

This paper provides a detailed description of the process used for developing the model, and the engineering design changes made that led to the model’s validation.

This paper documents an investigation of printed circuit board (PCB) failures due to edge burn outs. Electrical shorts were observed at late-stage environmental stress screening and electrical testing. Failed boards had burn marks at edges that were absent of components or surface circuitry.

Possible causes were high voltage arcing, temperature exposure, improper material cure, stress related to board de-panel, foreign material inclusions, and growth of conductive anodic filaments.

Failure analysis narrowed the cause to PCB dielectric material fracture. Cracks initiated at the edge of the board and propagated towards the center of the board, resulting in the formation of conductive bridges and electrical shorts between layers. As corrective action, the use of a mechanical de-panel machine was eliminated and replaced by edge routing; this has prevented additional failures.

A dynamic flex test was performed on a spacecraft instrument harness composed of multiple individual flex cables, with each flex cable containing multiple copper traces. The purpose of the test was to demonstrate the capability of the harness to survive the number of expected flex cycles during the planned mission with appropriate margin. However, during testing, increased trace resistances and open circuits were observed beginning at approximately 10% of the total number of planned flex cycles. This paper discusses the various proximate causes that contributed to increased and open resistance in the flex cables and the subsequent redesign, manufacturing, reliability, and quality-related changes that were instituted. An analysis process, including failure analysis, non-destructive evaluation, digital imaging correlation, and parametric modeling, will also be discussed. The paper will cover the development of a robust dynamic flex harness design and include recommendations to extend flex harness life; make changes to the flex harness life test; and improve flex cable manufacturing, quality, and reliability.