Today, more than 40% of cyber-attacks target IoT devices, and where attacks themselves are commercialized, it is becoming essential to take countermeasures against cyber-attacks, not only for defense but also for intrusion. Network management tools for such situations have already begun to appear on the market, IT experts are steadily taking measures and Business Continuity Plans (BCP) will be prepared.

Even with that, is important to understand if the factory is okay and if IT experts have considered an entry point from inside the factory.

When it comes to internal intrusion, the factory has its own characteristics, and special preparation is required. The easiest thing to understand is that the suspension of production at the factory is the suspension of shipment, which directly and quickly affects the business. At the factory, it is important to know how to limit potential damage to a limited range and how to recover quickly, which must be accelerated compared to the general approach. This is obvious to everyone involved in production, but IT experts have no way of knowing it.

In the experience of the author, when the production department hears the words "cyber-attack response BCP", they understand that cyber related issues should be taken up by the IT department, so all consideration are left up to the IT experts. As a result, special preparations were not made in consideration of the unique characteristics of the factory. It was therefore decided to strengthen the response later.

This paper, while referring to the actual results of the factory, will logically explain the measures to be taken based on the characteristics of the factory, and logically show the response in the event of a cyber-intrusion. The goals of this paper are to promote more measures for the entire supply chain and to help form the trust of the future electronic manufacturing industry.

For many years, the focus of the exchange of design and manufacturing data has been related to the reduction of lead-time in getting products to market, with the reduction of design-turns, engineering effort, and the number of inevitable mistakes associated with any manual manipulation of data. Today, the focus shifts to include consideration of security, in the wake of knowledge that sensitive data related to products and manufacturing have been accessed by unauthorized parties, leading to the rapid creation of cloned products, counterfeits, and even devices intended to play a part in a coordinated cyberattack.

At the same time however, there is the need for the extension of the use of data in a growing number of manufacturing automation applications on the shop-floor itself. The challenge is to make more use of data, such that automation of a greater number of engineering processes can be achieved, but in a way that ensures security and safety of the data and its value.

What went wrong, when did it happen and what have we learned? How often have we been confronted with these simple and direct words describing a situation where the outcome is undesirable! To address and understand the challenges and opportunities of export compliance in the PCB supply chain, one must first recognize and understand the underlying causes for the current situation. Or put simply, it is practically impossible to fix something, if you do not know what the problem is! This paper will address the opportunities cyber security and export compliance will bring to the actors in the PCB supply chain. It will also explain why the cost of these measurements are practically insignificant compared to the security, stability and long-term profitable commitment they will ensure.

Per- and polyfluoroalkyl substances (PFAS) is a class of fluoro-organic materials that is both ubiquitous and essential to the semiconductor manufacturing process as well as the downstream consumer electronics that semiconductors are incorporated into. PFAS and PFAS-containing articles are receiving unprecedented regulatory attention and are likely to be restricted to an end point of a ban of all non-essential uses. This presentation aims to provide an overview of these impending PFAS regulatory restrictions, how they are likely to impact the semiconductor and electronic system manufacturing industries, the strategies in place for identifying and justifying our ongoing essential uses, and a call to action for active participation within IPC and other appropriate electronics industry associations to create aligned industry voices and to ensure effective regulatory engagement strategies and control mechanisms going forward.

In this paper, we highlight the best practices for eco-design in electronics as presented during a multi-part learning series. The learning series was established as an interactive webinar-based experience in which eco-design leaders showcase their thought processes, strategies, successes, and failures in pursuing eco-design goals. This paper is intended for those who have experience in the design of electronics, are familiar with the concept and principles of eco-design, and are interested in advancing eco-design in their companies and their products. The learning series project stems from the work of the Sustainable Electronics Technology Integration Group at iNEMI, a group of electronics industry professionals that see that sustainability of the elec-tronics sector can be advanced by increasing circular product life cycles. How to implement circularity by design is a complex undertaking as it requires not only the right mindset, but tools to assess product life cycles, engineering skills to redesign products, engagement of the supply chain and ultimately also dealing with numerous constraints and risks. Therefore, this eco-design learning series aimed to identify a range of best practices in eco-design for a circular electronics economy. We covered industry segments including information and communications technology (ICT) infrastructure equipment, energy conversion and distribution components, automation technology and consumer products. We learned that the strategic approaches are manifold, and examples comprise better repairability enabled by a modular design, repurposing of smartphones at end of first life, increasing recycled material content (including both, post-industrial and post-consumer recycled material), shrinking pack-aging volumes by optimised design and by unbundling devices and accessories. Some of the main identified drivers for circular design are brand reputation, market demand and the implementation of new business models, but also policy developments. In some instances, there are sustainability trade-offs which must be considered, such as continuous progress in energy efficiency of network equipment, which leads to the insight that replacing network equipment from time to time lowers overall environ-mental impacts and that maximizing product lifetime may not always be an ideal strategy. A common approach is to base circular design on a thorough assessment of the environmental impacts over the full product lifecycle. A Life Cycle Assessment approach has been implemented by most of the leading companies in terms of eco-design, in some cases coupled with communicating environmental profiles through Environmental Product Declarations to provide some transparency for clients. Such an LCA approach works for small companies with only one product on the market, but also for larger players with a broad product portfolio.

Low Temperature Solder (LTS) is increasingly being used as a replacement for SAC305 solder alloy. Processing with LTS can reduce energy costs and impact on the environment while also reducing PCBA exposure to elevated temperatures, potentially reducing CTE mismatch stresses between PCBA and components and enhancing assembly reliability. Large BGA and LGA components are now being mounted with LTS. However, the low temperatures of the processes create numerous process challenges that are not experienced with SAC305, such as reduced effectiveness of flux during reflow. A study was conducted to better understand how process variables affect LGA solder joint formation. The effects of the type of LTS solder alloy, the stencil aperture geometry and thickness, and reflow profile on the quality of LTS LGA solder joints were examined. It was observed that solder joint quality is highly sensitive to solder volume and the flux and solder alloy combination that is used. Additionally, in conjunction with this study, work has been done on rework and touchup using LTS wire. One of the challenges is getting the wire supplied in spools due to the alloy’s brittle nature. To date, only one vendor has been able to provide LTS wire in a spool.

Keywords: Bismuth, Tin, LTS, SMT, Paste, Low Temp Solder, LGA, Rework

The 2017 International Electronics Manufacturing Initiatives (iNEMI) Board and Assembly Roadmap had forecast a 20% adoption rate of low-temperature solders (LTS) for board assembly by 2027. BiSn solders are the leading low-temperature candidates. However, the intrinsic brittleness of Bi restricts BiSn solders from drop-critical applications. An In-containing Sn-rich solder paste, referred to in this paper as "DFLT,” developed with a mixed powder technology—allows for reflow as low as 200°C, and shows excellent drop shock performance (comparable to or even better than traditional SAC305 [1]). DFLT has been successfully used in step soldering to interconnect two PCBs, pre-reflowed with traditional SAC solders, through an interposer in 5G mobile phone applications. A new generation of low-temperature lead-free solder pastes are being studied, targeted at further reducing the reflow peak temperature to 190°C while maintaining the drop shock performance and the thermal cycling reliability. One of the leading candidates, “874-71-1,” reflowed with either a 190°C or 200°C peak profile, has shown a comparable drop shock performance to DFLT (reflowed with a 200°C peak profile), which is at least two-orders-of-magnitude better than that of the eutectic BiSnAg. Both 874-71-1 (190°C and 200°C peak reflow) and DFLT(200°C peak reflow)have shown a similar characteristic life in the BGA192 thermal cycling test (-40/125°C), which is comparable to SAC305. The shear force of the 0805 chip resistor for DFLT (200°C peak profile), 874-71-1 (both 190°C and 200°C peak profiles) and SAC305 (245°C peak profile) become comparable after 2000 cycles TCT, although DFLT was stronger than 874-71-1 before TCT.

Key words: lead-free, solder, drop shock, low-temperature solder, mixed powder paste

Two challenges that advanced packaging suppliers are faced with during IC substrate fabrication are meeting the copper plating performance requirements and reducing manufacturing process costs. The copper plating must provide both high resolution and strict height uniformity within unit (WIU) and within a die/panel (WID). Plated features such as fine lines and pillars, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, that don’t require any special post treatment are highly desirable features for both redistribution layer (RDL) and pillar plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single step or from a single process bath. This flexibility allows fabricators to save on space and equipment.

In this paper, an electroplating (EPP) package, , is introduced to plate both RDL and pillars under different current densities in vertical continuous platers (VCP). The plating uniformity and coplanarity of both RDL fine lines and pillars was evaluated on a panel level.

The EPP package offered excellent coplanarity within a pattern unit for RDL plating. The variation in the plated height (or thickness) between fine lines and pads, of 5 and 50 μm widths respectively, was below 1.0 μm when using a current density of1.5 A/dm2 (ASD) for 66 minutes. For 10 μm wide lines, the plated copper thickness variation can be below 0.5 μm. The variation of plated thickness across 410 mm x 510 mm panels was below 1.0 μm, when the plated panel was measured at 3 points (top, middle, and bottom). The tops of the fine lines have defined, rectangular shapes. These types of profiles have excellent conductivity.

For pillar plating under higher current density, such as 5-10 ASD, the top of the pillars had slightly domed profiles. The pillars were very uniform within the die and within the panel.

Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit for thermal stress and warpage. The additives (wetter, leveler, and brightener) strongly influence the physical properties of the deposit. Copper deposited with the EPP package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change considerably during the bath aging, showing that the package has stable performance.

The reliability of both pillars and RDL features were evaluated via solder dip. The RDL features were dipped at 288°C, 6 times. The pillars were dipped at 288°C, 60 times. Neither feature showed any cracks or separation from the substrate.

For many years, the electroless copper process has been widely used by the PCB and package substrate industries, where a wide process window and proven product reliability has led to it being considered as the “industry standard” as a means of facilitating multilayer PCBs.

While there have been numerous incremental changes to improve overall capability and further widen its application range, the process as a whole may be considered by many to have remained “virtually unchanged”. Typically, an electroless copper process contains three major application steps, the “desmear” removes unwanted resin residues following the previous drilling operations, followed by a Palladium based “activation” which facilitates the subsequent “electroless copper “deposition. The performance and stability of the above general process has been widely reported, although one “issue” that to date remains unresolved, has been the identification of viable alternatives to Pd based activation. Such activator chemistries have seen a steady increase in their costs, up to the situation today, where Pd metal costs have become an appreciable contributor to overall electroless copper process costs. There have been some publications investigating alternatives to Pd, typically based on silver or copper, yet none appear to have been sufficiently successful to achieve any level of industrial acceptance.

In this paper, we discuss the technical issues that have been overcome in order to develop an activator system that is based on copper colloids. This solution has been shown to offer a process stability that has not been achieved with previous Cu based activation steps, where due to colloid agglomeration and/or oxidation, unacceptably short solution lifetimes have been encountered. We also characterize this fully Cu based process on a range of PCB and package substrate relevant dielectric materials, in order to demonstrate that the electroless copper process as a whole remains comparable to one using the existing Pd based technology, with no loss in physical or thermo-mechanical performance.

The High Density Packaging (HDP) user group has completed a project to evaluate dielectric conditions impacting the reliability of backdrilling escape vias under BGA via arrays. Large BGA sites are characterized by high density routing channels and finer pitch arrays of BGA escape vias. Backdrilling in these areas requires accurate drilling of the primary plated through vias and accurate secondary drilling or backdrilling to minimize the risk of incomplete removal of plated copper that could retain copper residues along the backdrilled surface. Backdrilling of the finer pitch via arrays also require well controlled board layer to layer registration to prevent exposing adjacent copper features and ensure sufficient dielectric encapsulation between the backdrilled via edge and copper inner layers1,2. This work evaluated the impact and risk of different levels of dielectric encapsulation after backdrilling by evaluation of three different backdrill process flows, a range of backdrill edge to adjacent copper spacings, and four different hole fill conditions. These parameters were evaluated and correlated with the following critical backdrill failure modes:

•Incomplete removal of plated copper within the via hole due to backdrill misregistration (copper wicking/ striping)

•Electrochemical migration between copper layers affected by backdrill misregistration, remaining residue, and laminate material manufacturing (temperature/humidity/bias testing per IPC TM-650, 2.6.25)

•Insufficient plating removal by backdrilling

This project aimed to determine the backdrill design parameters and PCB Fab manufacturing processing needed to ensure sufficient reliability of backdrilled BGA escape vias.

Key words: Backdrill, Electrochemical Migration, Backdrill to metal Isolation, Exposed Copper