Reliability assessment of Printed Wiring Boards and Assemblies using High Humidity at elevated temperatures has been done for a number of years. Many companies,including the IPC have published test requirements for products at high humidity at elevated temperatures. We currently perform testing to at least 10 different variations of these types of tests. In addition to variations in Temperature and Humidity,these tests also vary in whether a forcing potential is used during the test cycle. When a forcing voltage is used there are a variety of voltages specified. There are also differences in test voltage and whether the test voltage is applied in the same direction as the forcing voltage. This paper will describe the varying test methods used to conduct these environmental tests along with detailing the differences between them. It will highlight the different test patterns used and the benefits and limitations they represent. It will also encompass issues concerning test sample preparation,wiring,and placement within the test chamber that are not always addressed in the test method procedures.

A uniform transmission line is described electrically by a characteristic impedance and a time delay. From the length of the line and the time delay,the effective dielectric constant can be extracted. Two instruments are commonly used to measure these properties,a time domain reflectometer (TDR) and a vector network analyzer (VNA). In this paper,these techniques are reviewed. We show that an important factor influencing the quality of the measurements is the way the structure is probed. When using microprobes,the characteristic impedance and effective dielectric constant can be measured to within 1% accuracy. A collection of tips and tricks to improve the measurement accuracy are presented. Finally,the ability to accurately measure the dissipation factor of any laminate material up to 10 GHz,
with a VNA,is reviewed.

Automation,change and complexity have become the normal working environment in the PCB market. With this change has come the realization that high tech manufacturing,technological innovation and the fast paced world of the Electronics Interconnection Industry are intimately connected to rapid learning. In fact the very survival of
companies involved in the design and fabrication of PCB’s,their competitiveness,their ability to innovate and remain cost effective is directly linked to the speed and quality at which technical information is assimilated and applied by their workforces.

Inventory has been a hotly debated topic in many organizations. Since inventory is directly visible in company financials,there is a high degree of sensitivity to excessive inventory levels in the management ranks. Many organizations carefully track inventory turn ratios and benchmark themselves against key competitors. For some organizations a focus on “lean supply chains” with their high inventory turns have proven to be of substantial strategic value. Whenever the topic of inventory reduction surfaces,a discussion around the following tradeoff is bound to erupt: inventory reduction versus potential negative service level implications. This paper provides a fundamental and systematic approach for inventory optimization bringing these seemingly contradictory forces into unison. We will show a framework that can be applied,discuss two fundamental strategies to be used sequentially to reduce inventory and demonstrate the application of the principles in a case study. Reliance on IT solutions is also discussed. We briefly address the need of cash generation through inventory sell-offs even if doing so jeopardizes profitability. For many managers this seems like foolish executive action,but we will shed some light on the rational and demonstrate that in fact this action may represent sound business activity.

Solid Solder Deposit (SSD) technology was developed in the early and mid-1990's to improve first pass yields in the manufacture of electronic devices. As the trend towards finer pitch surface mount devices accelerated an alternative to conventional solder paste printing at assembly was desirable. Over 60% of defects in the assembly process have been attributed to the paste printing operation. These defects include solder shorts,insufficient solder/opens,and component skew. With the implementation of higher density devices,i.e. components with pad pitch spacing of .020" (Figure 1) and below,assembly yields declined dramatically. Yields were further exacerbated by the lack of planarity of the hot air solder leveling surface finish. Smaller pad geometries,as well as limitations in the solder leveling process and equipment,made it difficult to maintain a planar finish on double sided surface mount devices,particularly with the most prevalent vertical systems. A higher incidence of solder tails and shorts was more pronounced on fine pitch products. Further hot air leveling could cause thermal degradation,which may result in warp,delamination or solder mask related failures.

In many areas conductive polymers have already gained full acceptance as a reliable and qualitatively outstanding metallization process and as a true competitor for electroless Cu. In the paper presented the entire process sequence is explained,with the process not being a series of individual steps with individual functions,but a rather logical and most elegant sequence of interrelating chemical systems. Process details down to a molecular level are being revealed,information necessary to grasp the full meaning of each physical or chemical reaction occurring. Various process options are being discussed with a particular focus on the selection of monomers,acids in the polymerization step and buffer systems for the preceding MnO2 formation,knowledge which formed the basis for a recent process reengineering. Finally a series of HDI production results will be shown,demonstrating why conductive polymers are already the most successful PTH alternative to electroless Copper.

Processing thin core capacitor materials can be challenging,particularly those with non-reinforced dielectric less than 0.001” thick. Several processing steps require special attention to ensure the material is not damaged during manufacturing. Material storage and loading systems,conveyor systems and lamination systems must be capable of handling thin core material. Equipment modifications or special fixtures may be required in order to reduce the risk of jam-ups or fractured material. Special attention to cleanliness and the documentation of careful handling practices are also important. This paper will review some of the lessons we have learned about processing thin core capacitor materials from our participation in the NIST Advanced Embedded Passives Technology consortium.

A new versatile laser technology is available that is capable of working with both rigid and flexible boards using only one laser source. This system is based on a THG-UV laser (355 nm) and vector data software. This system can be used for drilling,cutting and structuring. Small and medium board manufacturers will be able to enter the HDI market with a minimum investment and a guaranty of high yields for each technology step. Various materials and combinations including glass fiber reinforced substrates can be drilled,cut and structured with the same equipment. This paper will introduce special applications in the area of micro via formation (minimum diameter of 30?m at 250
holes per second),laser direct structuring (minimum line widths of 0.8mil at 13.8 inches per second) and routing (compounds of various materials ) and will discuss the technological benefits.

Because of environmental concerns,elimination of lead from electronic components has been recently encouraged,and as a result,lead-free solders are frequently adopted for solder mounting. The OSP and HASL treatments have been primarily used for the majority of final surface treatments for PWB’s used for electronic components,while conventional electroless Ni/Au plating process has been used for the remainder. Lead-free solder mounting can lead to poor solderability in the case of some OSP-treated PWBs. The problems associated with HASL for the latest generation PWBs and packages is already well documented. Under the present conditions in which manufacturers are switching from conventional solders to lead-free solders and are beginning mass-production,this problem is being highlighted. Consequently,it is urgently required to establish a treatment method that can replace OSP treatment. This paper compares the solderability of immersion Ag,immersion Sn,and immersion Au plating that is treated directly on copper,and electroless Ni-P/Au plating,all of which are now attracting industry wide attentions as alternative surface treatments for PWB’s. The paper makes recommendations regarding the treatment method that supports future lead-free solder mounting.

The market for optical communication equipment and components has grown significantly since the early 1980s with growth rates exceeding 50% annually in the late 1990s. Although demand has dropped significantly since 2000,the underlying drivers for demand are still operating. This paper discusses the drivers for optoelectronic devices and optical PWBs,the major differences between IC packaging and optoelectronic device packaging,the emerging evolution of optical printed circuit board,and some of the opportunities for assembly and materials suppliers in these areas.