Because high performance products are limited in speed by packaging and interconnections,signal integrity analysis
and PWB simulation become nowadays very pressing and key issues. Taking into account these aspects,the
discontinuities of signal traces have also a more and more important contribution. For instance,in the past the
biggest problems regarding vias/via pads were only solderability and manufacturability. Today a via is understood
also as an electrical discontinuity and has to be properly designed and used.
The paper intends to present investigations realized in the labs of Center of Technological Electronics and
Interconnection Techniques (CETTI) from Bucharest,Romania,and focused on the influence of discontinuities and
parts of metallic interconnection networks on high-speed/high-frequency signals propagation. A computer modeling
was made and Spice models for a good compatibility with circuit simulators were obtained. S-,Y-,Z- parameters of
different kind of structures were calculated,too. The evaluation was realized by a modern MOM (Method of
Moments) electromagnetic simulation technique.1 At the end,a library of models for different discontinuities was
generated.

A concern in the manufacture of laminate PWB’s is the transfer of interior circuit patterns to the surface of the
board. This can lead to difficulties in forming the external circuitry. Typically,a number of identical boards are
assembled,separated by metal sheets (separator plates) and pressed. As layer counts have increased and the metal
separators have migrated towards thin aluminum,image transfer has become a bigger concern.
A study is conducted using Finite Element Analysis to examine the deformation and stress field within the laminate
and along the separator plates to better understand the mechanisms of image transfer. The analysis focuses on the
thermal growth of the composite during a fabrication cycle using a 2-d slice model of a “book” having orthotropic
linear elastic material property sets. A comparison is provided that illustrates order of magnitude agreement between
predicted FEA deformations and observations,and measurements made in a sample board.

This paper discusses two typical PTH failures – barrel cracking and post separation – induced by accelerated testing
or observed during manufacturing. Finite element models have been developed to help understand the effect of the
hole design parameters on the stress/strain state after thermal excursions.
An identical approach is then applied to study buried core vias – buried vias that connect from layer 2 to layer n-1 in
a Type II,high density interconnect (HDI) board. The impact of via fill material and its mechanical properties are
also presented. Additionally,the use of finite element analysis to perform life is discussed.

Motorola has developed a suite of technologies for embedding resistors,inductors,and capacitors in HDI printed
wiring boards. This paper describes the technology and presents a case study demonstrating the performance tradeoffs and design considerations that must be taken into account when embedding passive components into HDI PWB substrates. Furthermore,the benefit of embedded passives technology in adding “value” to the PWB,and in driving down size,cost,and part count for the OEM is illustrated.

The power attenuation of the optical fiber due to bends is investigated for the feasibility of the integration optical
fiber into PCBs.

A novel technology for embedding discrete capacitors in a mezzanine layer of an HDI PWB was developed and
implemented by Motorola in partnership with its PWB supply chain. The technology is based on the use of a
ceramic -filled positive type photo-dielectric to form discrete,embedded capacitors with capacitance densities
ranging from 10 to 30 pF/mm2. Capacitor test vehicles were designed,fabricated at multiple sites,tested,and used to
characterize the electrical performance and reliability of embedded mezzanine capacitor structures.
In this paper,the novel ceramic -filled dielectric capacitor fabrication process is outlined. Electrical tests are
reviewed,indicating a relative dielectric constant greater than 20,a loss tangent of less than 4%,and breakdown
voltages in excess of 100V for 11µm thick dielectrics. For reliability testing,minor variation in capacitance is
observable following multiple reflow cycles,liquid-to-liquid thermal shock,or air-to-air thermal cycling. A larger
shift in capacitance is observed following temperature-humidity storage,but the change is shown to be reversible.
Finally,two case studies are presented for RF modules using this embedded capacitor technology. In each case,area
usage is reduced while maintaining or reducing the overall module cost.

Design and processing of ceramic resistors and capacitors fired onto copper foil and embedded into FR4 circuit
boards are presented and discussed. Evolution of design guidelines and processing for embedded ceramics is
presented and discussed. Design tolerances are slightly larger for embedded ceramics because of the extra firing at
high temperatures experienced by the copper foil on which the resistors and capacitors are printed. Scaling of the
resistor and capacitor terminations must be done during print-and – etch operations.
Ceramic bodies are weak in tension and very strong in compression,so the most important processing precaution is
to minimize tension experienced by the resistors during high temperature firing and lamination. Somewhat reduced
lamination pressures is helpful. Limiting the size of resistors and capacitors is also helpful for capacitors. Size of
resistors is usually not a problem except for very small resistors below 10 mils in size Designs for these applications
include specially formulated pastes with thermal expansion behavior higher than is optimum for ceramic resistors
and capacitors on alumina substrates. In addition,protection of the ceramic components from the stress of the
lamination steps is desirable for the resistors. This is provided by encapsulating the resistors in a filled encapsulant
that reduces the expansion of the epoxy resin,and scatters the laser energy applied during resistor trimming,so that
the PWB itself is not harmed while being laser trimmed. Performance after processing appears excellent by usual
environmental tests; and board flexure encountered in bend tests does not appear to be a problem. To date,five mil
resistors appear too small to be screen printed with good CV and reliability. Ten mil and larger resistors are
adequately stable.

Various requirements have developed for printed wiring boards regarding the minimum spacing between features.
Creepage distances per UL-60950 call out 1.2mm for voltages up to 50v,and call out 1.4mm for voltages up to
100v,for products classified under pollution degree2 material group IIIa. IEC-664 has an altitude factor that needs
to be added for any product that is designed to go over 2000m altitude (for 3000m product there is an additional 14
percent). Tyco has established rules,which do not allow spacing on a product to go below certain minimums,
depending upon the class of product. The UL-1012 sets spacing limits for power supplies. Telcordia GR-78,Section
13.1.5,specifies minimum 10 megohms (10E+10 ohms) after 1,000 hours at 85 ?C,85% RH,and 100 VDC bias as
their minimum standard for electrochemical migration resistance testing for an expected 25 year minimum product
life requirement.
For many years Sun Microsystems has required a minimum 0.035 inches from drilled hole wall edge to drilled hole
wall edge for adjacent component holes,and minimum 0.025 inches from drilled hole wall edge to drilled hole wall
edge for adjacent through-hole vias,for certain standard voltage requirements. These standards for electrochemical
migration resistance between internal features or the printed wiring board,also known as resistance to conductive
anodic filament growth or "CAF" resistance,were based upon earlier AT&T data and actual experience by Sun
Microsystems with products in the field. Today more and more boards are being designed with relatively high I/O
PBGA packages,and associated with these devices are fairly dense arrangements of through-hole vias. The
increases in trace routing density are also driving higher via density. New connectors are being developed which
have higher pin density and/or need to carry higher voltages. As a result of these trends,there is strong interest in
more accurately evaluating the corresponding electrochemical migration or CAF reliability risk for a variety of
component and via plated-through hole-to-hole spacing.
The following paper documents some of the difficulties faced in developing a temperature/humidity/bias test and
data analysis methodology for comparing the electrochemical migration or CAF resistance of various standard and
alternate printed wiring board (PWB or PCB Fab) la minate materials. These findings should be of interest to those
evaluating material,design,and process effects on electrochemical migration resistance. Please note that this
electrochemical migration paper focuses on CAF formation,not surface dendritic growth.

This paper describes a process for plating of interconnects for advanced electronic modules. In contrast to traditional
chemical mediation of plating processes,this process is electrically mediated and does not rely on difficult to control
brighteners/levelers. The methodology for selection of the electric mediation parameters is based on considerations
of mass transfer and microprofiles/macroprofiles related to current distribution. This paper builds on earlier work by
incorporating plating cell/tank design issues including air agitation,eductor agitation,eductor orientation,back and
forth panel movement and knife-edge panel movement. Data for plating industry test panels containing microvias
and PTHs of approximately 4:1,10:1,and 20:1 aspect ratios are presented.

Many printed circuit board manufacturers report that the measured value of the differential impedance is a few ohms greater than the calculated value when the substrate is FR4. There may be several reasons for these differences:
???accuracy of the software used
???accurate knowledge of the track cross-section
???variation of the dielectric constant of the substrate
The software used by the authors,1 agrees,where possible,with good accurate theoretical impedance equations,particularly when the track thickness is zero. In addition,the new software referred to in Section 3,gives values of impedance which are within 25x10-2% of the values calculated by the software of Reference 1. Thus it is concluded that the calculated impedances are accurate.