Surface Insulation Resistance (SIR) Testing,has been used traditionally to characterise process materials,
particularly solder fluxes. Existing Surface Insulation resistance (SIR) test methods are outdated and unrepresentative of modern circuit technology1. A recent European research programme found that,using the existing international standards,the SIR value of a typical no-clean flux,could be over estimated by a factor of 10 when compared to a test using parameters representative of today’s technology. This new test method has,in addition,proved easier,cheaper and faster to perform; the equipment required is now readily available and a new IEC (Draft IEC 6-1189) process characterization specification is soon to be available. Here,in light of these European findings,an updated SIR test method is used to characterise a lead-free and VOC free electronic production process,including board surface finish,solder resist,paste,flux,wire and conformal coating – and using dummy components to more accurately determine their influence on the test protocol. The SIR test method is very simple in concept,and involves measuring the resistance across two inter-digitated comb patterns,whilst the sample is exposed to artificial ageing conditions of heat and high humidity. If a low SIR is seen on the test sample it is likely that the residues,if left on a PCA,will have a negative effect on the reliability of the circuit in the field. Whilst the principle is simple,the successful implementation of a test is not trivial. Historically the test was implemented simply with a single current metering instrument capable of measuring fractions of a micro-amp.
Modern test equipment allows frequent monitoring of a large number of samples at sensitivities of nano-amps or
better. This increased sensitivity has resulted in the European group’s ability to study the SIR values over a range of
track and pitch widths,using test patterns that are located underneath components. It was found that the coupons and voltage gradients defined by present standards,again lead to higher SIR values and fewer failure incidents,as compared to the results obtained for a coupon comprising a track width,pitch and voltage gradient combination representative of today’s technology. The Swedish research institute IVF and Delphi-Delco have shown that synergistic interactions with other process chemistries used in the manufacture of PCAs can affect the resulting SIR and hence the resultant reliability of the product. IPC J-STD-001B Appendix D does tackle the subject of process validation using SIR,but references the same SIR test methods for isolated flux qualification,that need updating.
Examples of the test results will be presented.

Vapor phase soldering is in discussion of the recent past. Some of the topics of our own work are presented in this paper,like the combination of vapor phase reflow soldering with wave soldering process. This combination makes it possible to solder printed circuit boards with SMT and THT components in one step. Additional the inert vapor atmosphere takes on the protection of liquid solder from oxidation. Another current development is an inline condensation soldering system. In a laboratory construction a lot of experiences were collected. The studies shows the importance of understanding the connection of partial pressure and temperature as well the mechanism of flow and heat transfer. First results were tested by soldering of true electronic assemblies and with lead free solders.

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller,lighter,and less expensive packages,and flip chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense step is not a typical process for an SMT factory,and demands additional capital equipment,floor space,cycle time and headcount. These additional investments,plus the inability to rework underfilled parts has limited wide scale implementation of flip chip technology. The National Institute of Standards and Technology Advanced Technology Program "Wafer Scale Applied Reworkable Fluxing Underfill for Direct Chip Attach" (NIST-ATP WARFU) was established to investigate the development of a flip chip underfill process that would be transparent to the SMT line. The program is supporting the successful development of fluxing,reworkable underfill materials and processes for direct application of the materials to die at the wafer level. While the application of underfill materials directly to the Wafer seems straight forward,many of the material requirements are incompatible with each other. For instance,the necessity of dicing the wafer using water is not compatible with the use of uncured epoxy materials. In addition,the incorporation of fluxing materials into the bulk underfill is known to degrade long-term stability at room temperature. This needs to be addressed,as the stated goal of the program is to provide at least 6 months of on part life prior to use. The methods and materials used to address these concerns are described in the paper.

Lead-free wave soldering was studied in this work using Sn/Ag/Cu alloy. A process DOE was developed,with three
variables (solder bath temperature,conveyor speed,and soldering atmosphere),using a dual wave system. Nine no clean flux systems,including alcohol- and water-based types,were included in the evaluation. A specially designed “Lead-Free Solder Test Vehicle”,which has various types of components,was used in the experiments. Both organic solderability preservative (OSP) and electroless nickel/ immersion gold (Ni/Au,or ENIG) surface finishes\ were studied. Soldering performance (solder ball,bridging,wetting and hole filling,and flux residues) was used as the responses for the DOE. In addition,dross formation was measured at different solder bath temperatures and atmospheres. Regarding the connector-type component,a pad design giving the best soldering performance was evaluated based on the DOE results. Finally,a confirmation run with the optimum flux and process parameters was carried out using the Sn/Ag/Cu solder,and a comparative run was made with the Sn/Pb solder alloy and the no-clean flux used in production. The soldering results between the two runs indicate that with optimum flux and process parameters,it is possible to achieve acceptable process performance with the Sn/Ag/Cu alloy. Mechanical testing and cross-section study were used to verify the solder joint integrity and compare the mechanical performance between the Sn/Ag/Cu and Sn/Pb solder joints.

In-line inspection equipment has become common place in the PCB assembly industry. This equipment is intended to both eliminate defects at an early stage of production and to be used as a process control tool to prevent these defects from occurring in the first place. In practice the full benefits of the applied Statistical Process Control (SPC) methods have typically not been realized even though many of today’s Automated Optical Inspection (AOI) systems come equipped with built-in SPC tools. In this paper we will discuss how a contract manufacturer and an AOI vendor have worked together to develop SPC tools and methods for solder paste printing using a 3D solder paste inspection system.

The use of Chip Scale Packaging (CSP) is rapidly expanding,particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However,mechanical shock and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. This paper examines the assembly process with capillary and fluxing underfills. Issues of solder paste versus flux only,solder flux residue cleaning and reworkability are investigated with the capillary flow underfills. Fluxing underfills eliminate the issues of flux-underfill compatibility,but require placement into a predispensed underfill. Voiding during placement is discussed. To evaluate the relative performance of the underfills,a drop test was performed and the results are presented. All of the underfills significantly improved the reliability in the drop test compared to non-underfilled parts. Processes such as cleaning or rework that improved the adhesion of the underfill to the PWB solder mask further improved drop test reliability

Automated X-ray inspection (AXI) is more often a part of an effective test strategy for today's PCBAs1 because of the benefits it provides manufacturers in meeting challenges resulting from2:
•?Continued product miniaturization amid increased product functionality
•?Increased time to market and time to volume pressures
•?Growth in outsourcing and contract manufacturing
The structural defect coverage provided by AXI is complementary to electrical test; AXI helps to increase overall fault coverage when used in combination with flying probe,in-circuit and functional test methods.3,4 Despite the benefits offered by AXI,new users sometimes struggle with its implementation due to a lack of experience and procedures on how to optimize the inspection process to achieve stated performance targets. Common concerns among this user group include high false failure rates and defect escape rates. Because AXI is a relatively new test technology,many users are unaware of best practice use-models and continuous improvement methodologies that can be used to stabilize the inspection process and attain targeted performance goals for both defect detection and false failure rates. This paper will demonstrate procedures,use-models and continuous improvement methodologies that AXI users should consider when establishing norms for their own operational practices. Like any manufacturing process,appropriate procedures and metrics must be put in place to attain performance goals. Once suitable operational procedures are in place,even new manufacturing technologies like AXI will perform within predictable and acceptable performance limits. The recommendations and best practices discussed in this paper are derived from the practical experiences of the authors in their direct work with AXI processes in volume production environments.

Three epoxy systems were evaluated for physical and optical properties. The three systems chosen for the study were selected on the basis of their optical clarity,color and chemistry. Three distinctly different chemistries were chosen,aromatic epoxy- amine cured. Aromatic epoxy- anhydride cured and cycloaliphatic epoxy- anhydride cured. All three systems remained optically clear and water-white after full cure. The three selected systems were tested for physical properties,adhesion and light transmission properties. Light transmission was measured after thermal andHumidity Exposure. Adhesion was measured afterHumidity Exposure only. Both of the epoxy-anhydride systems performed well in optical properties but poorer in adhesion as compared to the epoxy-amine system. The aromatic epoxy-amine system discolored badly during thermal exposure at 100 C. Data generated from this work will be used in selecting clear encapsulating materials for photonics applications. No single system offers optimal performance in all areas. The best compromise material is the aromatic epoxyanhydride system.

The purpose of this study is to understand the capability of both AOI and AXI machines and where the two could be combined to increase the inspection coverage,reduce the overall cycle time of the inspection process and provide the most cost effective solution.

Application of solder paste by using stencil-printing process is a commonly used method for high volume electronics circuits manufacturing. This process has proved to be the fastest and most cost-efficient. Unfortunately this method has shown its limitation for components with pitch smaller than 300 micron. For these components an alternative method is the tacky flux process. It takes place directly on the fine pitch component mounter equipped with flux-dipping unit. The process stages can be described as follows:
1. Pick up component;
2. Dip component bumps in the flux unit;
3. Place component on the substrate.
The expectation is that this assembly process will allow handling of components with bump pitches down to 100 micron. Therefore it can be extremely interesting for assembly of Flip Chips with eutectic bumps. When FCs with eutectic bumps are placed in solder paste,the position of most components is corrected during reflow,due to the self-alignment of the liquid solder. Likewise,when components with eutectic bumps are placed in flux,the position of most of them is also corrected,due to self-alignment,but the placement accuracy requirements have not been fully investigated. This article presents the research findings with reference to the relationship between placement accuracy and formation of solder joints for components with eutectic bumps placed in flux.